📄 flash.c~
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//******************************************************************************
// Copyright (C) 2005, ZEMTEC.COM All Rights Reserved.
//
// AT25F1024 读写控制程序
//
//
// VCC
// _________________ |
// P5_4-> -o|/CS VCC|---
// | |
// P5_7-> --|SO /HOLD|o- <- P5_5
// | AT25F1024 |
// P5_4-> -o|/WP SCK|-- <- P5_2
// | |
// --|GND SI|-- <- P5_6
// | -----------------
// GND
//
// VCC
// _________________ |
// PG1 -> -o|/CS VCC|---
// | |
// PB3 <- --|SO /HOLD|o- <- VCC
// | AT25F1024 |
// PG0 -> -o|/WP SCK|-- <- PC7
// | |
// --|GND SI|-- <- PC6
// | -----------------
// GND
//
// MCU: ATMEGA128L
//
// AUTHOR: ecc
// E-MAIL: mgyuli@zemtec.com
// Created: April 2005
//******************************************************************************
#include <mega128.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "typedef.h"
#include "app.h"
#include "attention.h"
#include "Flash.h"
#include "g20modem.h"
#include "g20serialdrv.h"
#include "rtc.h"
#include "serialdrv.h"
#include "timer.h"
#include "UDP.h"
#include "protocol.h"
#include "lcdzk.h"
#define PIN0 0x01
#define PIN1 0x02
#define PIN2 0x04
#define PIN3 0x08
#define PIN4 0x10
#define PIN5 0x20
#define PIN6 0x40
#define PIN7 0x80
#define WREN 0x06
#define WRDI 0x04
#define RDSR 0x05
#define WRSR 0x01
#define READ 0x03
#define PROGRAM 0x02
#define SECTORERASE 0x52
#define CHIPERASE 0x62
#define RDID 0x15
#define CS1_EN PORTG &= ~PIN1
#define CS1_DEN PORTG |= PIN1
#define CS2_EN PORTG &= ~PIN1
#define CS2_DEN PORTG |= PIN1
/*#define CS2_EN PORTG &= ~PIN2
#define CS2_DEN PORTG |= PIN2*/
#define SCK_0 PORTG &= ~PIN1
#define SCK_1 PORTG |= PIN1
#define SI_0 PORTC &= ~PIN2
#define SI_1 PORTC |= PIN2
volatile unsigned char flash_hl_swith = FALSE;
/*void flash_set_switch(unsigned long laddr)
{
if(laddr > 0x1ffff)
{
flash_hl_swith = TRUE;
}
else
{
flash_hl_swith = FALSE;
}
}*/
/* init flash */
void inital_flash(void)
{
PORTG |= 0x07;
DDRG |= 0x07;
PORTG |= 0x05;
PORTC &= ~0xC0;
DDRC |= 0xC0;
}
/* read byte from Flash MSB */
unsigned char ReadByte(void)
{
unsigned char nLoop;
unsigned char tmp;
unsigned char ret;
tmp = 0x00;
ret = 0x00;
for(nLoop = 0; nLoop < 8; nLoop ++)
{
ret <<=1;
SCK_0;
SCK_1;
tmp = PINB;
if((tmp & PIN3) == PIN3)
{
ret |= 0x01;
}
}
return ret;
}
/* write BYTE to Flash MSB */
void WriteByte(unsigned char ch)
{
unsigned char nLoop;
for(nLoop = 0; nLoop < 8; nLoop++)
{
SI_0;
if((ch & 0x80) == 0x80)
{
SI_1;
}
SCK_0;
SCK_1;
ch <<= 1;
}
SCK_0;
}
void flash_init_pin()
{
SI_0;
SCK_0;
}
/* chip erase */
void ChipErase()
{
GetReady();
SetWriteEnable();
GetReady();
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(CHIPERASE);
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
}
/* Sector ERASE */
void SectorErase(unsigned char *pAdd)
{
GetReady();
SetWriteEnable();
GetReady();
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(SECTORERASE);
WriteByte(pAdd[0]);
WriteByte(pAdd[1]);
WriteByte(pAdd[2]);
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
}
/* read data from memory */
void ReadData(unsigned char *pBuf, unsigned char *pAdd)
{
unsigned int a;
a = 5;
GetReady();
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(READ);
WriteByte(pAdd[0]);
WriteByte(pAdd[1]);
WriteByte(pAdd[2]);
for(a = 0; a < 60; a ++)
{
*(pBuf + a) = ReadByte();
}
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
}
/* write data into memory */
void WriteData(unsigned char *pBuf, unsigned char *pAdd)
{
unsigned char nloop;
GetReady();
SetWriteEnable();
GetReady();
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(PROGRAM);
WriteByte(pAdd[0]);
WriteByte(pAdd[1]);
WriteByte(pAdd[2]);
//while(*pBuf != 0x00)
for(nloop = 0; nloop < 60; nloop ++)
{
WriteByte(*(pBuf++));
}
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
}
/* Write Status Register */
void WriteWRSR(unsigned char BP0, unsigned char BP1)
{
unsigned char status;
status = (unsigned char)0x00;
if((unsigned char)1 == BP0)
{
status |= 0x04;
}
if((unsigned char)1 == BP1)
{
status |= 0x08;
}
GetReady();
SetWriteEnable();
GetReady();
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(WRSR);
WriteByte(status);
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
}
/* Reset write enable lath */
void ResetWriteEnable()
{
GetReady();
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(WRDI);
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
}
/* read manufacture ID */
void ReadRDID(void)
{
volatile unsigned char tmp[2];
GetReady();
tmp[0] = (unsigned char)0x00;
tmp[1] = (unsigned char)0x00;
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(RDID);
tmp[0] = ReadByte();
tmp[1] = ReadByte();
tmp[0] = tmp[0];
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
flash_init_pin();
}
/* set write enable latch */
void SetWriteEnable()
{
GetReady();
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(WREN);
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
}
/* read status register */
unsigned char ReadRDSR(void)
{
unsigned char ret;
ret = (unsigned char)0x00;
flash_init_pin();
if(flash_hl_swith == TRUE)
{
CS2_DEN;
CS1_EN;
}
else
{
CS1_DEN;
CS2_EN;
}
WriteByte(RDSR);
ret = ReadByte();
ret = ret;
if(flash_hl_swith == TRUE)
CS1_DEN;
else
CS2_DEN;
return ret;
}
/* is flash ready */
void GetReady()
{
unsigned int nLoop;
while((ReadRDSR() & 0x01) == 0x01)
{
wdr();
nLoop = 3000;
while(nLoop -- > 0);
}
}
/*void storage_init()
{
// BYTE nYear = 0, nMonth = 0, nDay=0;
// BYTE nHour = 0, nMin = 0, nSec = 0;
// ombro_reset();
//save last data
//get the first data pointer
// clk_cur_pCLK = clk_getfirst();
// clk_cur_pCLK->bUsed = FALSE;
// clk_cur_pCLK->nAddr = 0x000;
return;
// Clk_getcurclk(&nYear, &nMonth, &nDay, &nHour, &nMin, &nSec);
// clk_cur_pCLK->nYear = nYear;
// clk_cur_pCLK->nMonth = nMonth;
// clk_cur_pCLK->nDay = nDay;
}*/
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