app.c

使用avr--cc2420模块程序,需要原理图的联系 QQ:120304948

#include <mega128.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <delay.h>
#include <spi.h>

#include "typedef.h"
#include "serialdrv.h"

#include "app.h"

#include "timer.h"
#include "rtc.h"
#include "cc2420.h"
#include "18B20.h"
#include "intp.h"


bit system_initial_flag;
bit study_ok = 1;

unsigned char timer_init_code[8] = 
{
	0x30, 0x31, 0x16, 0x23, 0x03, 0x05, 0x07, 0x00
};

void system_initial()
{
	system_initial_flag = FALSE;
	
	CPU_init();
/*	
    ts_init();
    
    delay_ms(1000);
    wdr();
    
    ts_FindDevices();
    
   	rtc_init();
//	usart0_init();
*/
	timer_init();
    sp_init();
    wdr();
    	
    delay_ms(100);
    cc2420_initial();	
    cc2420_ready();
    INTP_init();	
   	
    wdr();
	EINT;
    timer_delay(100);

	EINT;
	system_initial_flag = TRUE;
    wdr();
    
}

void main(void)
{		
//	rtc_set_flag = TRUE;
	
	system_initial();
	
//    v_Set1302(timer_init_code);
    		
//	rtc_set_flag = FALSE;

	workingloop();
}


void workingloop()
{

	while(1)
	{
        wdr();
        if (receive_ok)
        {
            receive_ok = 0;
            cc2420_deal();
//			WORK_LED = !WORK_LED; 
        }
        if ((study_ok == 0) && (int_start == 1)) 
        {
            sp_proc();
        }
//        cc2420_test();
        wdr();
        if (all_sending)
        {
            all_sending = FALSE;
            
            EIMSK=0x00;     //0x0D  //0x01
            cc2420_ready();
            wdr();
            delay_ms(10);
   	        CSn=0;
            spi(SFLUSHRX);
            spi(SFLUSHRX);
            CSn=1;
            receive_ok = 0;
    		EIFR=0x0D;
            if (study_ok)
                EIMSK=0x01;     //0x0D  //0x01 
            else 
            { 
                EIMSK=0x0D;     //0x0D  //0x01   
                int_start = 0;
                int_num = 0;
        		count=0;
            }

            data_proc();
			WORK_LED = !WORK_LED; 
        }
/*        wdr();
        if (reset_cc2420)
        {
//            EIMSK=0x00;     //0x0D  //0x01 
//            TIMSK=0x00;  
//            while (1);
            reset_cc2420 = FALSE;
            EIMSK=0x00;     //0x0D  //0x01
            cc2420_ready();
            wdr();
            delay_ms(100);
   	        CSn=0;
            spi(SFLUSHRX);
            spi(SFLUSHRX);
            CSn=1;
            receive_ok = 0;
    		EIFR=0x0D;
            if (study_ok)
                EIMSK=0x01;     //0x0D  //0x01 
            else 
            { 
                EIMSK=0x0D;     //0x0D  //0x01   
                int_start = 0;
                int_num = 0;
        		count=0;
            }
//			WORK_LED = !WORK_LED; 
        }*/
	}
}

void CPU_init(void)
{
// Input/Output Ports initialization
// Port A initialization
// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In 
// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T 
PORTA=0x00;
DDRA=0x00;

// Port B initialization
// Func7=In Func6=In Func5=In Func4=Out Func3=In Func2=Out Func1=Out Func0=Out 
// State7=P State6=P State5=P State4=1 State3=P State2=1 State1=1 State0=1 
PORTB=0xFF;
DDRB=0x17;

// Port C initialization
// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In 
// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T 
PORTC=0x00;
DDRC=0x00;

// Port D initialization
// Func7=Out Func6=In Func5=Out Func4=In Func3=In Func2=In Func1=Out Func0=In 
// State7=1 State6=T State5=0 State4=T State3=T State2=T State1=0 State0=T 
PORTD=0x80;     //0x82
DDRD=0xA2;

// Port E initialization
// Func7=In Func6=In Func5=Out Func4=In Func3=In Func2=In Func1=In Func0=In 
// State7=T State6=T State5=0 State4=T State3=T State2=T State1=T State0=T 
PORTE=0x00;
DDRE=0x20;

// Port F initialization
// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In 
// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T 
PORTF=0x00;
DDRF=0x00;

// Port G initialization
// Func4=In Func3=In Func2=In Func1=In Func0=In 
// State4=T State3=T State2=T State1=T State0=T 
PORTG=0x00;
DDRG=0x00;

// Analog Comparator initialization
// Analog Comparator: Off
// Analog Comparator Input Capture by Timer/Counter 1: Off
ACSR=0x80;
SFIOR=0x00;

// Watchdog Timer initialization
// Watchdog Timer Prescaler: OSC/2048k
#pragma optsize-
WDTCR=0x1F;
WDTCR=0x0F;
#ifdef _OPTIMIZE_SIZE_
#pragma optsize+
#endif

}