📄 w99av.h
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//**************************************************************************
// define the address of I/O registers
#if IO == IO_PCI
#define AIR0 __wW99AVBaseIO
#define PSR0 __wW99AVBaseIO // Chuan.908
#define AIR1 (__wW99AVBaseIO + 0x1)
#define PSR1 (__wW99AVBaseIO + 0x1) // Chuan.908
#define AIR2 (__wW99AVBaseIO + 0x2)
#define PSR2 (__wW99AVBaseIO + 0x2) // Chuan.908
#define AIR3 (__wW99AVBaseIO + 0x3)
#define PSR3 (__wW99AVBaseIO + 0x3) // Chuan.908
#define DPR0 (__wW99AVBaseIO + 0x4)
#define DPR1 (__wW99AVBaseIO + 0x5)
#define DPR2 (__wW99AVBaseIO + 0x6)
#define DPR3 (__wW99AVBaseIO + 0x7)
#define IBDPR0 (__wW99AVBaseIO + 0x8)
#define IBFR (__wW99AVBaseIO + 0x8) // Chuan.908
#define GBDR0 (__wW99AVBaseIO + 0x9) // Chuan.908
#define GBDR1 (__wW99AVBaseIO + 0xA) // Chuan.908
#define GBDR2 (__wW99AVBaseIO + 0xB) // Chuan.908
#define IADPR0 (__wW99AVBaseIO + 0xC)
#define IAFR (__wW99AVBaseIO + 0xC) // Chuan.908
#define GBAR (__wW99AVBaseIO + 0xD) // Chuan.908
#define DSAR0 (__wW99AVBaseIO + 0x10)
#define DSAR1 (__wW99AVBaseIO + 0x11)
#define DSAR2 (__wW99AVBaseIO + 0x12)
#define CDPR (__wW99AVBaseIO + 0x13)
#define BSR0 (__wW99AVBaseIO + 0x14)
#define BSR1 (__wW99AVBaseIO + 0x15)
#define CACR (__wW99AVBaseIO + 0x16)
#define CAR (__wW99AVBaseIO + 0x17)
#define OFSR CAR
#define CER (__wW99AVBaseIO + 0x18)
#define CMR CER
#define AIR0_BYTE __wW99AVBaseIOByte
#define PSR0_BYTE __wW99AVBaseIOByte // Chuan.908
#define AIR1_BYTE (__wW99AVBaseIOByte + 0x1)
#define PSR1_BYTE (__wW99AVBaseIOByte + 0x1) // Chuan.908
#define AIR2_BYTE (__wW99AVBaseIOByte + 0x2)
#define PSR2_BYTE (__wW99AVBaseIOByte + 0x2) // Chuan.908
#define AIR3_BYTE (__wW99AVBaseIOByte + 0x3)
#define PSR3_BYTE (__wW99AVBaseIOByte + 0x3) // Chuan.908
#define DPR0_BYTE (__wW99AVBaseIOByte + 0x4)
#define DPR1_BYTE (__wW99AVBaseIOByte + 0x5)
#define DPR2_BYTE (__wW99AVBaseIOByte + 0x6)
#define DPR3_BYTE (__wW99AVBaseIOByte + 0x7)
#define IBDPR0_BYTE (__wW99AVBaseIOByte + 0x8)
#define IBFR_BYTE (__wW99AVBaseIOByte + 0x8) // Chuan.908
#define GBDR0_BYTE (__wW99AVBaseIOByte + 0x9) // Chuan.908
#define GBDR1_BYTE (__wW99AVBaseIOByte + 0xA) // Chuan.908
#define GBDR2_BYTE (__wW99AVBaseIOByte + 0xB) // Chuan.908
#define IADPR0_BYTE (__wW99AVBaseIOByte + 0xC)
#define IAFR_BYTE (__wW99AVBaseIOByte + 0xC) // Chuan.908
#define GBAR_BYTE (__wW99AVBaseIOByte + 0xD) // Chuan.908
#define DSAR0_BYTE (__wW99AVBaseIOByte + 0x10)
#define DSAR1_BYTE (__wW99AVBaseIOByte + 0x11)
#define DSAR2_BYTE (__wW99AVBaseIOByte + 0x12)
#define CDPR_BYTE (__wW99AVBaseIOByte + 0x13)
#define BSR0_BYTE (__wW99AVBaseIOByte + 0x14)
#define BSR1_BYTE (__wW99AVBaseIOByte + 0x15)
#define CACR_BYTE (__wW99AVBaseIOByte + 0x16)
#define CAR_BYTE (__wW99AVBaseIOByte + 0x17)
#define OFSR_BYTE CAR_BYTE
#define CER_BYTE (__wW99AVBaseIOByte + 0x18)
#define CMR_BYTE CER_BYTE
#else
#define W9922QFIO 0xFF80
#define basep *(volatile BYTE xdata *) W9922QFIO
#define AIR0 *(volatile BYTE xdata *) W9922QFIO
#define PSR0 *(volatile BYTE xdata *) W9922QFIO // Chuan.908
#define AIR1 *(volatile BYTE xdata *) (W9922QFIO + 0x1)
#define PSR1 *(volatile BYTE xdata *) (W9922QFIO + 0x1) // Chuan.908
#define AIR2 *(volatile BYTE xdata *) (W9922QFIO + 0x2)
#define PSR2 *(volatile BYTE xdata *) (W9922QFIO + 0x2) // Chuan.908
#define AIR3 *(volatile BYTE xdata *) (W9922QFIO + 0x3)
#define PSR3 *(volatile BYTE xdata *) (W9922QFIO + 0x3) // Chuan.908
#define DPR0 *(volatile BYTE xdata *) (W9922QFIO + 0x4)
#define DPR1 *(volatile BYTE xdata *) (W9922QFIO + 0x5)
#define DPR2 *(volatile BYTE xdata *) (W9922QFIO + 0x6)
#define DPR3 *(volatile BYTE xdata *) (W9922QFIO + 0x7)
#define IBDPR0 *(volatile BYTE xdata *) (W9922QFIO + 0x8)
#define IBFR *(volatile BYTE xdata *) (W9922QFIO + 0x8) // Chuan.908
#define GBDR0 *(volatile BYTE xdata *) (W9922QFIO + 0x9) // Chuan.908
#define GBDR1 *(volatile BYTE xdata *) (W9922QFIO + 0xA) // Chuan.908
#define GBDR2 *(volatile BYTE xdata *) (W9922QFIO + 0xB) // Chuan.908
#define IADPR0 *(volatile BYTE xdata *) (W9922QFIO + 0xC)
#define IAFR *(volatile BYTE xdata *) (W9922QFIO + 0xC) // Chuan.908
#define GBAR *(volatile BYTE xdata *) (W9922QFIO + 0xD) // Chuan.908
#define DACIO *(volatile BYTE xdata *) (W9922QFIO + 0x24) //CoCo.28AF
#define DSAR0 *(volatile BYTE xdata *) (W9922QFIO + 0x10)
#define DSAR1 *(volatile BYTE xdata *) (W9922QFIO + 0x11)
#define DSAR2 *(volatile BYTE xdata *) (W9922QFIO + 0x12)
#define CDPR *(volatile BYTE xdata *) (W9922QFIO + 0x13)
#define BSR0 *(volatile BYTE xdata *) (W9922QFIO + 0x14)
#define BSR1 *(volatile BYTE xdata *) (W9922QFIO + 0x15)
#define CACR *(volatile BYTE xdata *) (W9922QFIO + 0x16)
#define CAR *(volatile BYTE xdata *) (W9922QFIO + 0x17)
#define OFSR CAR
#define CER *(volatile BYTE xdata *) (W9922QFIO + 0x18)
#define CMR CER
// wyc.277a, for HKC code.
#define EXT_CS1_PORT *(volatile BYTE xdata *) (W9922QFIO + 0x40) // EXT_CS1_PORT HCC //Jeff 20020701
#define EXT_CS2_PORT *(volatile BYTE xdata *) (W9922QFIO + 0x41) // EXT_CS2_PORT HCC //Jeff 20020701
#endif
//*************************************************************************
//*****************************************************
// define System Operating Registers
#define PCR 0x80
#define STCR 0x81
#define ISR 0x82
#define PFCR ISR
#define IER 0x83
#define VBRR 0x85
#define MCCR 0x84
#define ACCR 0x87
#define EMUCR 0x8f
#define GPCR1 0x94
#define GPCR2 0x95
#define CCPCR 0x98 //Chip Configuration Pull-up Control Register for 908S only
#define DEBR 0x88
#define IOAR 0x89
#define UPR 0x8a
#define ABRR 0x8b
#define PWRCR 0x8c
#define ICCR PWRCR
#define SECIDR 0x8d
#define PIOCR 0x8e //CoCo.28af
#define SCRR 0x90
#define ATAPI_SCR 0x91 //CoCo.28af
#define UCPR1 0x92 //CoCo.28af
#define UCPR2 0X93 //CoCo.28af
#define FCR0 0xa0
#define FCR1 0xa1
#define FCR2 0xa2
#define FCR3 0xa3
#define FCR4 0xa4
#define PLLCTL 0xa5
#define TSTCTL 0xa6
#define PAR_TBL 0xa7
//*****************************************************
//*****************************************************
// define Internal RISC operating Registers
#define PARFIFOCTLR 0x43
#define BSFIFOREMR 0x45
#define PARFIFOREMR 0x46
#define SUBP1R 0x48
#define SUBP2R 0x49
#define ABUFSIZER 0x4a
#define VPTSHR 0x4b
#define VPTSLR 0x4c
#define DVDCTLR 0x4d
#define DVDIDHR 0x4e
#define DVDIDLR 0x4f
#define VBICTLR 0x50
#define CHXR 0x51
#define CHYR 0x52
#define COFFSETR 0x59
#define DCCTLR 0x69
#define VBUFSIZER 0x6d
#define SP_INDEX 0x74
#define SP_DATA 0x75
#define OSDCTLR 0x78
#define STC_0 0x7a
#define STC_1 0x7b
#define SPOGTPTSHR 0x7e
#define SPOGTPTSLR 0x7f
#define RMADRR 0x90
#define AVIDR 0x91
#define PCMCNTR 0x96
#define WBAR 0x97
#define ADCMR 0x98
#define AUDIOCFG0R 0x99
#define AUDIOCFG1R 0x9a
#define AUDIOCFG2R 0x9b
#define DYNAMICSR 0x9c
#define IEC958DELAYR 0x9d
#define PCMSCALER 0x9e
#define DMDATAR 0x9f
#define DMINDEXR 0xa0
#define BRR 0xa1
#define RBAR 0xa2
#define WAIRCR 0xa3
#define DSPCTLR 0xa4
#define CICR 0xa5
#define CDSR 0xa6
#define CDIENR 0xa7
#define DCR 0xa8
#define DICR 0xa9
#define DIENR 0xaa
#define DSR 0xab
#define VBUNDERSETR 0xaf
#define CFR 0xb3
#define TRICKR 0xb4
#define ABREMAINDERR 0xb5
#define ABOVERSETR 0xb6
#define ABUNDERSETR 0xb7
#define PARCTLR 0xb8
#define PARSTATUSR 0xb9
#define SYNCMODER 0xbd
#define VBREMAINDERR 0xbe
#define VBOVERSETR 0xbf
// wyc2.80, some new TV encoder registers for CT908
#define TVE_CR0 0xC0
#define TVE_CR1 0xC1
#define CCTX_LN_O 0xC2
#define CC_D 0xC4
#define WSS_D_O 0xC5
#define WSS_D_E 0xC6
#define GAIN_YC 0xC7
#define GAIN_CAV 0xCE
#define FAIN_G 0xCF
#define WSS_D_O 0xC5
#define MV0 0xC8
#define MV1 0xC9
#define MV2 0xCA
#define MV3 0xCB
#define MV4 0xCC
#define MV5 0xCD
#define BSFORMATR 0xc4
//LJY1.11, support CDDA anti-shock
#define ABUFBAKREMR 0xCE //denote the Abak remainder for CDDA
#define BCUVR 0xd6
#define BCYR 0xd7
#define GCAR 0xd8
#define FCR 0xd9
#define HDSR 0xda
#define HDWR 0xdb
#define LAR 0xdc
#define PALDATAR 0xde
#define PALINDEXR 0xdf
#define SPVDSHDSR 0xe0
#define VBIVCSHCSR 0xe3
#define VDSVDWR 0xe4
#define VDRR VDSVDWR
#define YUVOFFSETR 0xe5
#define NVSUBIDR 0xe6
#define VCR 0xe7
#define PCTR 0xf0
#define DIR1R 0xf1
#define PCRR 0xf4
#define DIR0R 0xf6
//*****************************************************
//*****************************************************
// define S/W reset type
#define W99AV_RESET_VIDEO 0
#define W99AV_RESET_AUDIO 1
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