memory.tan.qmsg

来自「fpga与单片机的接口程序」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "iCLK register register state.sCS always0~0 340.02 MHz Internal " "Info: Clock \"iCLK\" Internal fmax is restricted to 340.02 MHz between source register \"state.sCS\" and destination register \"always0~0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.155 ns + Longest register register " "Info: + Longest register to register delay is 1.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.sCS 1 REG LCFF_X1_Y3_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N23; Fanout = 2; REG Node = 'state.sCS'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { state.sCS } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.616 ns) 1.047 ns always0~95 2 COMB LCCOMB_X1_Y3_N8 1 " "Info: 2: + IC(0.431 ns) + CELL(0.616 ns) = 1.047 ns; Loc. = LCCOMB_X1_Y3_N8; Fanout = 1; COMB Node = 'always0~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.047 ns" { state.sCS always0~95 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.155 ns always0~0 3 REG LCFF_X1_Y3_N9 9 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.155 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { always0~95 always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.724 ns ( 62.68 % ) " "Info: Total cell delay = 0.724 ns ( 62.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.431 ns ( 37.32 % ) " "Info: Total interconnect delay = 0.431 ns ( 37.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.155 ns" { state.sCS always0~95 always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.155 ns" { state.sCS always0~95 always0~0 } { 0.000ns 0.431ns 0.000ns } { 0.000ns 0.616ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK destination 2.865 ns + Shortest register " "Info: + Shortest clock path from clock \"iCLK\" to destination register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns iCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { iCLK } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns iCLK~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { iCLK iCLK~clkctrl } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns always0~0 3 REG LCFF_X1_Y3_N9 9 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { iCLK~clkctrl always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl always0~0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK source 2.865 ns - Longest register " "Info: - Longest clock path from clock \"iCLK\" to source register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns iCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { iCLK } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns iCLK~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { iCLK iCLK~clkctrl } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns state.sCS 3 REG LCFF_X1_Y3_N23 2 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N23; Fanout = 2; REG Node = 'state.sCS'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { iCLK~clkctrl state.sCS } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl state.sCS } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl state.sCS } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl always0~0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl state.sCS } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl state.sCS } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.155 ns" { state.sCS always0~95 always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.155 ns" { state.sCS always0~95 always0~0 } { 0.000ns 0.431ns 0.000ns } { 0.000ns 0.616ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl always0~0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl state.sCS } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl state.sCS } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { always0~0 } {  } {  } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "always0~0 CS iCLK 4.644 ns register " "Info: tsu for register \"always0~0\" (data pin = \"CS\", clock pin = \"iCLK\") is 4.644 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.549 ns + Longest pin register " "Info: + Longest pin to register delay is 7.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns CS 1 PIN PIN_58 4 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_58; Fanout = 4; PIN Node = 'CS'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CS } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.786 ns) + CELL(0.651 ns) 7.441 ns always0~95 2 COMB LCCOMB_X1_Y3_N8 1 " "Info: 2: + IC(5.786 ns) + CELL(0.651 ns) = 7.441 ns; Loc. = LCCOMB_X1_Y3_N8; Fanout = 1; COMB Node = 'always0~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.437 ns" { CS always0~95 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.549 ns always0~0 3 REG LCFF_X1_Y3_N9 9 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.549 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { always0~95 always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.763 ns ( 23.35 % ) " "Info: Total cell delay = 1.763 ns ( 23.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.786 ns ( 76.65 % ) " "Info: Total interconnect delay = 5.786 ns ( 76.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.549 ns" { CS always0~95 always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.549 ns" { CS CS~combout always0~95 always0~0 } { 0.000ns 0.000ns 5.786ns 0.000ns } { 0.000ns 1.004ns 0.651ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK destination 2.865 ns - Shortest register " "Info: - Shortest clock path from clock \"iCLK\" to destination register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns iCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { iCLK } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns iCLK~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { iCLK iCLK~clkctrl } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns always0~0 3 REG LCFF_X1_Y3_N9 9 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { iCLK~clkctrl always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl always0~0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.549 ns" { CS always0~95 always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.549 ns" { CS CS~combout always0~95 always0~0 } { 0.000ns 0.000ns 5.786ns 0.000ns } { 0.000ns 1.004ns 0.651ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl always0~0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "iCLK odata\[6\] always0~0 8.573 ns register " "Info: tco from clock \"iCLK\" to destination pin \"odata\[6\]\" through register \"always0~0\" is 8.573 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK source 2.865 ns + Longest register " "Info: + Longest clock path from clock \"iCLK\" to source register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns iCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { iCLK } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns iCLK~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { iCLK iCLK~clkctrl } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns always0~0 3 REG LCFF_X1_Y3_N9 9 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { iCLK~clkctrl always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl always0~0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.404 ns + Longest register pin " "Info: + Longest register to pin delay is 5.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns always0~0 1 REG LCFF_X1_Y3_N9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.288 ns) + CELL(3.116 ns) 5.404 ns odata\[6\] 2 PIN PIN_5 0 " "Info: 2: + IC(2.288 ns) + CELL(3.116 ns) = 5.404 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'odata\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.404 ns" { always0~0 odata[6] } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 57.66 % ) " "Info: Total cell delay = 3.116 ns ( 57.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.288 ns ( 42.34 % ) " "Info: Total interconnect delay = 2.288 ns ( 42.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.404 ns" { always0~0 odata[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.404 ns" { always0~0 odata[6] } { 0.000ns 2.288ns } { 0.000ns 3.116ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl always0~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl always0~0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.404 ns" { always0~0 odata[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.404 ns" { always0~0 odata[6] } { 0.000ns 2.288ns } { 0.000ns 3.116ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "state.sdRD CS iCLK -4.266 ns register " "Info: th for register \"state.sdRD\" (data pin = \"CS\", clock pin = \"iCLK\") is -4.266 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK destination 2.865 ns + Longest register " "Info: + Longest clock path from clock \"iCLK\" to destination register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns iCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { iCLK } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns iCLK~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { iCLK iCLK~clkctrl } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns state.sdRD 3 REG LCFF_X1_Y3_N27 3 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N27; Fanout = 3; REG Node = 'state.sdRD'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { iCLK~clkctrl state.sdRD } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl state.sdRD } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl state.sdRD } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.437 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns CS 1 PIN PIN_58 4 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_58; Fanout = 4; PIN Node = 'CS'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CS } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.788 ns) + CELL(0.537 ns) 7.329 ns state~26 2 COMB LCCOMB_X1_Y3_N26 1 " "Info: 2: + IC(5.788 ns) + CELL(0.537 ns) = 7.329 ns; Loc. = LCCOMB_X1_Y3_N26; Fanout = 1; COMB Node = 'state~26'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.325 ns" { CS state~26 } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.437 ns state.sdRD 3 REG LCFF_X1_Y3_N27 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.437 ns; Loc. = LCFF_X1_Y3_N27; Fanout = 3; REG Node = 'state.sdRD'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { state~26 state.sdRD } "NODE_NAME" } } { "memory.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹 (2)/memory.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.649 ns ( 22.17 % ) " "Info: Total cell delay = 1.649 ns ( 22.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.788 ns ( 77.83 % ) " "Info: Total interconnect delay = 5.788 ns ( 77.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.437 ns" { CS state~26 state.sdRD } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.437 ns" { CS CS~combout state~26 state.sdRD } { 0.000ns 0.000ns 5.788ns 0.000ns } { 0.000ns 1.004ns 0.537ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { iCLK iCLK~clkctrl state.sdRD } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { iCLK iCLK~combout iCLK~clkctrl state.sdRD } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.437 ns" { CS state~26 state.sdRD } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.437 ns" { CS CS~combout state~26 state.sdRD } { 0.000ns 0.000ns 5.788ns 0.000ns } { 0.000ns 1.004ns 0.537ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}