memory.tan.rpt

fpga与单片机的接口程序

+-------+--------------+------------+------+------------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-----------+----------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To       ; From Clock ;
+-------+--------------+------------+-----------+----------+------------+
; N/A   ; None         ; 8.573 ns   ; always0~0 ; odata[6] ; iCLK       ;
; N/A   ; None         ; 8.455 ns   ; always0~0 ; odata[5] ; iCLK       ;
; N/A   ; None         ; 8.039 ns   ; always0~0 ; odata[3] ; iCLK       ;
; N/A   ; None         ; 7.819 ns   ; always0~0 ; odata[2] ; iCLK       ;
; N/A   ; None         ; 7.720 ns   ; always0~0 ; odata[7] ; iCLK       ;
; N/A   ; None         ; 7.407 ns   ; always0~0 ; odata[4] ; iCLK       ;
; N/A   ; None         ; 7.332 ns   ; always0~0 ; odata[1] ; iCLK       ;
; N/A   ; None         ; 6.992 ns   ; always0~0 ; odata[0] ; iCLK       ;
+-------+--------------+------------+-----------+----------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To         ; To Clock ;
+---------------+-------------+-----------+------+------------+----------+
; N/A           ; None        ; -4.266 ns ; CS   ; state.sdRD ; iCLK     ;
; N/A           ; None        ; -4.342 ns ; CS   ; state.Idle ; iCLK     ;
; N/A           ; None        ; -4.344 ns ; CS   ; state.sCS  ; iCLK     ;
; N/A           ; None        ; -4.378 ns ; CS   ; always0~0  ; iCLK     ;
+---------------+-------------+-----------+------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Sep 24 16:35:41 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off memory -c memory --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "iCLK" is an undefined clock
Info: Clock "iCLK" Internal fmax is restricted to 340.02 MHz between source register "state.sCS" and destination register "always0~0"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.155 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N23; Fanout = 2; REG Node = 'state.sCS'
            Info: 2: + IC(0.431 ns) + CELL(0.616 ns) = 1.047 ns; Loc. = LCCOMB_X1_Y3_N8; Fanout = 1; COMB Node = 'always0~95'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.155 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'
            Info: Total cell delay = 0.724 ns ( 62.68 % )
            Info: Total interconnect delay = 0.431 ns ( 37.32 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "iCLK" to destination register is 2.865 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'
                Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'
                Info: Total cell delay = 1.806 ns ( 63.04 % )
                Info: Total interconnect delay = 1.059 ns ( 36.96 % )
            Info: - Longest clock path from clock "iCLK" to source register is 2.865 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'
                Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N23; Fanout = 2; REG Node = 'state.sCS'
                Info: Total cell delay = 1.806 ns ( 63.04 % )
                Info: Total interconnect delay = 1.059 ns ( 36.96 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "always0~0" (data pin = "CS", clock pin = "iCLK") is 4.644 ns
    Info: + Longest pin to register delay is 7.549 ns
        Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_58; Fanout = 4; PIN Node = 'CS'
        Info: 2: + IC(5.786 ns) + CELL(0.651 ns) = 7.441 ns; Loc. = LCCOMB_X1_Y3_N8; Fanout = 1; COMB Node = 'always0~95'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.549 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'
        Info: Total cell delay = 1.763 ns ( 23.35 % )
        Info: Total interconnect delay = 5.786 ns ( 76.65 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "iCLK" to destination register is 2.865 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'
        Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'
        Info: Total cell delay = 1.806 ns ( 63.04 % )
        Info: Total interconnect delay = 1.059 ns ( 36.96 % )
Info: tco from clock "iCLK" to destination pin "odata[6]" through register "always0~0" is 8.573 ns
    Info: + Longest clock path from clock "iCLK" to source register is 2.865 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'
        Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'
        Info: Total cell delay = 1.806 ns ( 63.04 % )
        Info: Total interconnect delay = 1.059 ns ( 36.96 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.404 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N9; Fanout = 9; REG Node = 'always0~0'
        Info: 2: + IC(2.288 ns) + CELL(3.116 ns) = 5.404 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'odata[6]'
        Info: Total cell delay = 3.116 ns ( 57.66 % )
        Info: Total interconnect delay = 2.288 ns ( 42.34 % )
Info: th for register "state.sdRD" (data pin = "CS", clock pin = "iCLK") is -4.266 ns
    Info: + Longest clock path from clock "iCLK" to destination register is 2.865 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'iCLK'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'iCLK~clkctrl'
        Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X1_Y3_N27; Fanout = 3; REG Node = 'state.sdRD'
        Info: Total cell delay = 1.806 ns ( 63.04 % )
        Info: Total interconnect delay = 1.059 ns ( 36.96 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.437 ns
        Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_58; Fanout = 4; PIN Node = 'CS'
        Info: 2: + IC(5.788 ns) + CELL(0.537 ns) = 7.329 ns; Loc. = LCCOMB_X1_Y3_N26; Fanout = 1; COMB Node = 'state~26'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.437 ns; Loc. = LCFF_X1_Y3_N27; Fanout = 3; REG Node = 'state.sdRD'
        Info: Total cell delay = 1.649 ns ( 22.17 % )
        Info: Total interconnect delay = 5.788 ns ( 77.83 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Sep 24 16:35:42 2007
    Info: Elapsed time: 00:00:01