memory.map.rpt

fpga与单片机的接口程序

;     -- normal mode                          ; 4         ;
;     -- arithmetic mode                      ; 0         ;
; Total registers                             ; 4         ;
; I/O pins                                    ; 13        ;
; Maximum fan-out node                        ; always0~0 ;
; Maximum fan-out                             ; 9         ;
; Total fan-out                               ; 27        ;
; Average fan-out                             ; 1.29      ;
+---------------------------------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |memory                    ; 4 (4)             ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 13   ; 0            ; |memory             ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------+
; State Machine - |memory|state                    ;
+------------+------------+-----------+------------+
; Name       ; state.Idle ; state.sCS ; state.sdRD ;
+------------+------------+-----------+------------+
; state.Idle ; 0          ; 0         ; 0          ;
; state.sdRD ; 1          ; 0         ; 1          ;
; state.sCS  ; 1          ; 1         ; 0          ;
+------------+------------+-----------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Source assignments for Top-level Entity: |memory ;
+----------------+-------+------+------------------+
; Assignment     ; Value ; From ; To               ;
+----------------+-------+------+------------------+
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~         ;
+----------------+-------+------+------------------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |memory ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type                                          ;
+----------------+-------+-----------------------------------------------+
; H_TOTAL        ; 512   ; Integer                                       ;
; Idle           ; 00000 ; Binary                                        ;
; sdRD           ; 00001 ; Binary                                        ;
; shRD           ; 01000 ; Binary                                        ;
; sCS            ; 10000 ; Binary                                        ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Sep 24 16:35:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off memory -c memory
Info: Found 1 design units, including 1 entities, in source file memory.v
    Info: Found entity 1: memory
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Info: Elaborating entity "memory" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at memory.v(11): object "H_TOTAL" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at memory.v(17): object "shRD" assigned a value but never read
Warning (10034): Output port "ready" at memory.v(7) has no driver
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:u2"
Warning: Reduced register "odata[6]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "odata[4]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "odata[2]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "odata[0]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "Reset_Delay:u2|oRST" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "Reset_Delay:u2|oRST" with stuck data_in port to stuck value VCC
Info: Power-up level of register "odata[7]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "odata[7]~reg0" with stuck data_in port to stuck value VCC
Info: Power-up level of register "odata[5]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "odata[5]~reg0" with stuck data_in port to stuck value VCC
Info: Power-up level of register "odata[3]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "odata[3]~reg0" with stuck data_in port to stuck value VCC
Info: Power-up level of register "odata[1]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "odata[1]~reg0" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "always0~1" merged to single register "always0~0"
    Info: Duplicate register "always0~3" merged to single register "always0~0"
    Info: Duplicate register "always0~5" merged to single register "always0~0"
    Info: Duplicate register "always0~7" merged to single register "always0~0"
    Info: Duplicate register "always0~9" merged to single register "always0~0"
    Info: Duplicate register "always0~11" merged to single register "always0~0"
    Info: Duplicate register "always0~13" merged to single register "always0~0"
Info: State machine "|memory|state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|memory|state"
Info: Encoding result for state machine "|memory|state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "state.Idle"
        Info: Encoded state bit "state.sCS"
        Info: Encoded state bit "state.sdRD"
    Info: State "|memory|state.Idle" uses code string "000"
    Info: State "|memory|state.sdRD" uses code string "101"
    Info: State "|memory|state.sCS" uses code string "110"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ready" stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "RD"
    Warning: No output dependent on input pin "trigger"
Info: Implemented 17 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 9 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings
    Info: Processing ended: Mon Sep 24 16:35:29 2007
    Info: Elapsed time: 00:00:01