📄 fw.lst
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224 4
225 4 // 8051 activity will resume here due to USB bus or W
-akeup# pin activity.
226 4 EZUSB_Resume(); // If source is the Wakeup# pin, si
-gnal the host to Resume.
227 4 TD_Resume();
228 4 }
229 3 }
230 2 TD_Poll();
231 2 }
232 1 }
233
234 // Device request parser
235 void SetupCommand(void)
236 {
237 1 void *dscr_ptr;
238 1
239 1 switch(SETUPDAT[1])
240 1 {
241 2 case SC_GET_DESCRIPTOR: // *** Get Descript
-or
242 2 if(DR_GetDescriptor())
243 2 switch(SETUPDAT[3])
244 2 {
245 3 case GD_DEVICE: // Device
246 3 SUDPTRH = MSB(pDeviceDscr);
247 3 SUDPTRL = LSB(pDeviceDscr);
248 3 break;
249 3 case GD_DEVICE_QUALIFIER: // Device Qual
-ifier
250 3 SUDPTRH = MSB(pDeviceQualDscr);
251 3 SUDPTRL = LSB(pDeviceQualDscr);
252 3 break;
253 3 case GD_CONFIGURATION: // Configuration
254 3 SUDPTRH = MSB(pConfigDscr);
255 3 SUDPTRL = LSB(pConfigDscr);
256 3 break;
C51 COMPILER V6.14 FW 10/06/2006 14:23:48 PAGE 6
257 3 case GD_OTHER_SPEED_CONFIGURATION: // Other Speed
-Configuration
258 3 SUDPTRH = MSB(pOtherConfigDscr);
259 3 SUDPTRL = LSB(pOtherConfigDscr);
260 3 break;
261 3 case GD_STRING: // String
262 3 if(dscr_ptr = (void *)EZUSB_GetStringDscr(SETUPD
-AT[2]))
263 3 {
264 4 SUDPTRH = MSB(dscr_ptr);
265 4 SUDPTRL = LSB(dscr_ptr);
266 4 }
267 3 else
268 3 EZUSB_STALL_EP0(); // Stall End Point 0
269 3 break;
270 3 default: // Invalid request
271 3 EZUSB_STALL_EP0(); // Stall End Point 0
272 3 }
273 2 break;
274 2 case SC_GET_INTERFACE: // *** Get Interface
275 2 DR_GetInterface();
276 2 break;
277 2 case SC_SET_INTERFACE: // *** Set Interface
278 2 DR_SetInterface();
279 2 break;
280 2 case SC_SET_CONFIGURATION: // *** Set Configur
-ation
281 2 DR_SetConfiguration();
282 2 break;
283 2 case SC_GET_CONFIGURATION: // *** Get Configur
-ation
284 2 DR_GetConfiguration();
285 2 break;
286 2 case SC_GET_STATUS: // *** Get Status
287 2 if(DR_GetStatus())
288 2 switch(SETUPDAT[0])
289 2 {
290 3 case GS_DEVICE: // Device
291 3 EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr;
292 3 EP0BUF[1] = 0;
293 3 EP0BCH = 0;
294 3 EP0BCL = 2;
295 3 break;
296 3 case GS_INTERFACE: // Interface
297 3 EP0BUF[0] = 0;
298 3 EP0BUF[1] = 0;
299 3 EP0BCH = 0;
300 3 EP0BCL = 2;
301 3 break;
302 3 case GS_ENDPOINT: // End Point
303 3 EP0BUF[0] = *(BYTE xdata *) epcs(SETUPDAT[4]) &
-bmEPSTALL;
304 3 EP0BUF[1] = 0;
305 3 EP0BCH = 0;
306 3 EP0BCL = 2;
307 3 break;
308 3 default: // Invalid Command
309 3 EZUSB_STALL_EP0(); // Stall End Point 0
310 3 }
311 2 break;
312 2 case SC_CLEAR_FEATURE: // *** Clear Feature
313 2 if(DR_ClearFeature())
C51 COMPILER V6.14 FW 10/06/2006 14:23:48 PAGE 7
314 2 switch(SETUPDAT[0])
315 2 {
316 3 case FT_DEVICE: // Device
317 3 if(SETUPDAT[2] == 1)
318 3 Rwuen = FALSE; // Disable Remote Wakeup
319 3 else
320 3 EZUSB_STALL_EP0(); // Stall End Point 0
321 3 break;
322 3 case FT_ENDPOINT: // End Point
323 3 if(SETUPDAT[2] == 0)
324 3 {
325 4 *(BYTE xdata *) epcs(SETUPDAT[4]) &= ~bmEPSTA
-LL;
326 4 EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] );
327 4 }
328 3 else
329 3 EZUSB_STALL_EP0(); // Stall End Point 0
330 3 break;
331 3 }
332 2 break;
333 2 case SC_SET_FEATURE: // *** Set Feature
334 2 if(DR_SetFeature())
335 2 switch(SETUPDAT[0])
336 2 {
337 3 case FT_DEVICE: // Device
338 3 if(SETUPDAT[2] == 1)
339 3 Rwuen = TRUE; // Enable Remote Wakeup
340 3 else if(SETUPDAT[2] == 2)
341 3 // Set Feature Test Mode. The core handles t
-his request. However, it is
342 3 // necessary for the firmware to complete the
- handshake phase of the
343 3 // control transfer before the chip will ente
-r test mode. It is also
344 3 // necessary for FX2 to be physically disconn
-ected (D+ and D-)
345 3 // from the host before it will enter test mo
-de.
346 3 break;
347 3 else
348 3 EZUSB_STALL_EP0(); // Stall End Point 0
349 3 break;
350 3 case FT_ENDPOINT: // End Point
351 3 *(BYTE xdata *) epcs(SETUPDAT[4]) |= bmEPSTALL;
352 3 break;
353 3 }
354 2 break;
355 2 default: // *** Invalid Command
356 2 if(DR_VendorCmnd())
357 2 EZUSB_STALL_EP0(); // Stall End Point 0
358 2 }
359 1
360 1 // Acknowledge handshake phase of device request
361 1 EP0CS |= bmHSNAK;
362 1 }
363
364 // Wake-up interrupt handler
365 void resume_isr(void) interrupt WKUP_VECT
366 {
367 1 EZUSB_CLEAR_RSMIRQ();
368 1 }
369
C51 COMPILER V6.14 FW 10/06/2006 14:23:48 PAGE 8
370
C51 COMPILER V6.14 FW 10/06/2006 14:23:48 PAGE 9
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION main (BEGIN)
; SOURCE LINE # 106
; SOURCE LINE # 107
; SOURCE LINE # 111
0000 E4 CLR A
0001 F500 R MOV j+03H,A
0003 F500 R MOV j+02H,A
0005 F500 R MOV j+01H,A
0007 F500 R MOV j,A
; SOURCE LINE # 116
0009 C200 R CLR Sleep
; SOURCE LINE # 117
000B C200 R CLR Rwuen
; SOURCE LINE # 118
000D C200 R CLR Selfpwr
; SOURCE LINE # 119
000F C200 R CLR GotSUD
; SOURCE LINE # 122
0011 120000 E LCALL TD_Init
; SOURCE LINE # 130
0014 7E00 E MOV R6,#HIGH DeviceDscr
0016 7F00 E MOV R7,#LOW DeviceDscr
0018 8E00 R MOV pDeviceDscr,R6
001A 8F00 R MOV pDeviceDscr+01H,R7
; SOURCE LINE # 131
001C 750000 E MOV pDeviceQualDscr,#HIGH DeviceQualDscr
001F 750000 E MOV pDeviceQualDscr+01H,#LOW DeviceQualDscr
; SOURCE LINE # 132
0022 750000 E MOV pHighSpeedConfigDscr,#HIGH HighSpeedConfigDscr
0025 750000 E MOV pHighSpeedConfigDscr+01H,#LOW HighSpeedConfigDscr
; SOURCE LINE # 133
0028 750000 E MOV pFullSpeedConfigDscr,#HIGH FullSpeedConfigDscr
002B 750000 E MOV pFullSpeedConfigDscr+01H,#LOW FullSpeedConfigDscr
; SOURCE LINE # 134
002E 750000 E MOV pStringDscr,#HIGH StringDscr
0031 750000 E MOV pStringDscr+01H,#LOW StringDscr
; SOURCE LINE # 136
0034 900000 E MOV DPTR,#USBCS
0037 E0 MOVX A,@DPTR
0038 30E71F JNB ACC.7,?C0001
; SOURCE LINE # 137
; SOURCE LINE # 138
003B 850000 R MOV pConfigDscr,pHighSpeedConfigDscr
003E 850000 R MOV pConfigDscr+01H,pHighSpeedConfigDscr+01H
; SOURCE LINE # 139
0041 850000 R MOV pOtherConfigDscr,pFullSpeedConfigDscr
0044 850000 R MOV pOtherConfigDscr+01H,pFullSpeedConfigDscr+01H
; SOURCE LINE # 140
0047 00 NOP
0048 00 NOP
0049 00 NOP
; SOURCE LINE # 141
004A 900000 E MOV DPTR,#EP6BCH
004D 7402 MOV A,#02H
004F F0 MOVX @DPTR,A
; SOURCE LINE # 142
0050 00 NOP
0051 00 NOP
0052 00 NOP
C51 COMPILER V6.14 FW 10/06/2006 14:23:48 PAGE 10
; SOURCE LINE # 143
0053 E4 CLR A
0054 900000 E MOV DPTR,#EP6BCL
0057 F0 MOVX @DPTR,A
; SOURCE LINE # 144
0058 800C SJMP ?C0002
005A ?C0001:
; SOURCE LINE # 146
; SOURCE LINE # 147
005A 850000 R MOV pConfigDscr,pFullSpeedConfigDscr
005D 850000 R MOV pConfigDscr+01H,pFullSpeedConfigDscr+01H
; SOURCE LINE # 148
0060 850000 R MOV pOtherConfigDscr,pHighSpeedConfigDscr
0063 850000 R MOV pOtherConfigDscr+01H,pHighSpeedConfigDscr+01H
; SOURCE LINE # 149
0066 ?C0002:
; SOURCE LINE # 151
0066 EE MOV A,R6
0067 54E0 ANL A,#0E0H
0069 7003 JNZ $ + 5H
006B 020000 R LJMP ?C0003
; SOURCE LINE # 152
; SOURCE LINE # 153
006E 750000 R MOV IntDescrAddr,#00H
0071 750080 R MOV IntDescrAddr+01H,#080H
; SOURCE LINE # 154
0074 7E00 E MOV R6,#HIGH DeviceDscr
0076 7F00 E MOV R7,#LOW DeviceDscr
0078 8E00 R MOV ExtDescrAddr,R6
007A 8F00 R MOV ExtDescrAddr+01H,R7
; SOURCE LINE # 155
007C C3 CLR C
007D 7400 E MOV A,#LOW UserDscr
007F 9F SUBB A,R7
0080 FF MOV R7,A
0081 7400 E MOV A,#HIGH UserDscr
0083 9E SUBB A,R6
0084 CF XCH A,R7
0085 2402 ADD A,#02H
0087 CF XCH A,R7
0088 3400 ADDC A,#00H
008A FE MOV R6,A
008B E4 CLR A
008C 8F00 R MOV DevDescrLen+03H,R7
008E 8E00 R MOV DevDescrLen+02H,R6
0090 F500 R MOV DevDescrLen+01H,A
0092 F500 R MOV DevDescrLen,A
; SOURCE LINE # 156
0094 F500 R MOV i+03H,A
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