📄 twicreg.h
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// [7] reserved
// [6:0] set the luma peak white detection's AGC nominal peak white value.
// this value is added to 128 and then the result is multiplied by 4.
// Default = 0x0A(10d)
#define AGC_PKNO_REG 0x10
#define AGC_PKNO_DEFAULT 0x0A
#define AGC_PKNO 0x27
// AGC peak and gate control, 0x11
// [7]
#define AGC_PKGT_CTRL_REG 0x11
#define AGC_PKGT_CTRL_DEFAULT 0xB9
#define AGC_PKGT_CTRL 0xB9
// Chroma DTO incremental 0, 1, 2, 3, 0x18~0x1B
// [7] 1: fix chroma DTO at center frequency
// 0: Chroma DTO assigned by registers
// [6] reserved
// [29:0]
#define CHROMA_DTO0_REG 0x18
#define CHROMA_DTO0_DEFAULT 0x21
#define CHROMA_DTO1_REG 0x19
#define CHROMA_DTO1_DEFAULT 0xF0
#define CHROMA_DTO2_REG 0x1A
#define CHROMA_DTO2_DEFAULT 0x7C
#define CHROMA_DTO3_REG 0x1B
#define CHROMA_DTO3_DEFAULT 0x0F
#define CHROMA_DTO0 0x21
#define CHROMA_DTO1 0xF0
#define CHROMA_DTO2 0x7C
#define CHROMA_DTO3 0x1F
// Active video horizontal start time, 0x2E
//
// Active video horizontal width, 0x2F
// Add 640 to this register
#define HACT_START_REG 0x2E
#define HACT_START_DEFAULT 0x82
#define HACT_WIDTH_REG 0x2F
#define HACT_WIDTH_DEFAULT 0x50
#define HACT_START 0x82
#define HACT_WIDTH 0x50
//Active video vertical start, 0x30
//
// Active video vertical height, 0x31
// add 384 to this register, specify the height by the number of half lines
#define VACT_START_REG 0x30
#define VACT_START_DEFAULT 0x22
#define VACT_HEIGHT_REG 0x31
#define VACT_HEIGHT_DEFAULT 0x61
#define VACT_START 0x24
#define VACT_HEIGHT 0x61
// Vsync time constant, 0x39
// [7] set the output field polarity
// 0: field=1 for odd fields, field=0 for even fields (default)
// 1: field=0 for odd fields, field=1 for even fields
// [6] flip even/odd fields
// [5] delay detection of even fields by 1 vertical line (default=0)
// [4] delay detection of odd fields by 1 vertical line (default=0)
// [3:2] control the field detection logic (default=10)
// [1:0] set the vertical PLL time constant
// 00: fast. only useful if the vloop_cntl is not 11. Internal values are 2 & 1
// 01: moderate. Internal values are 1 & 1/4
// 10: slow. Internal values are 1/2 & 1/16 (default)
// 11: very slow. Most useful for noisy signals. Internal values are 1/4 & 1/2
#define VSYNC_TIME_REG 0x39
#define VSYNC_TIME_DEFAULT 0x0A
#define VSYNC_TIME 0x8A
// Soft reset, 0x3F
// [7:1] reserved
// [0] write 1 to reset initial values for comb filter
#define SOFT_RESET_REG 0x3F
#define SOFT_RESET 0x01
// Luminance peaking control, 0x80
//
#define LUMINANCE_PKCTRL_REG 0x80
#define LUMINANCE_PKCTRL_DEFAULT 0x04
#define LUMINANCE_PKCTRL 0x05
// Comb filter configuration, 0x82
// [7] reserved
// [6] used to reduce phase-error artifacts in the comb filter's luma-path.
// should be set for VCR signals. Default=1
// [5] When set, this will turn on the pal_perr(P2_82[6]) when VCR signal is detected
// Default=0
// [4] used to select the bandpass filter used in the comb-filter.
// Should be set to 1 for PAL mode. Default=0
// [3:2] reserved
// [1:0] used to determine how many incorrect lines are used for the pal switch
// circuit before switching. Use a higher level for noisy signals.
// Default=2
#define COMB_FILTERCFG_REG 0x82
#define COMB_FILTERCFG_DEFAULT 0x42
#define COMB_FILTERCFG 0x42
//===========================================================
//===========================================================
//===========================================================
#define ADC_PLLDIV_H 0x16//0x00
#define ADC_PLLDIV_L 0x15//0x01
#define ADC_VCOCP 0x17//0x02
#define ADC_PHASE 0x03
#define ADC_CLPL 0x04
#define ADC_CLDU 0x05
#define ADC_FHSOPW 0x06
#define ADC_RGAIN 0x07
#define ADC_GGAIN 0x08
#define ADC_BGAIN 0x09
#define ADC_ROFF 0x0A
#define ADC_ROFF_DEFAULT 0x0A
#define ADC_GOFF 0x0B
#define ADC_BOFF 0x0C
#define ADC_FBHSYNC 0x0E
#define ADC_TEST_MODE 0x0F
#define SLTSSYNC 0x80
#define CKBYP 0x01
#define ADC_SYNC_ROUT 0x10
#define HREFSEL 0x08
#define CSTSEL 0x04
#define ADCVSSEL 0x02
/* Sync Detection Regs */
#define CS_CFG 0x12
#define CS_RST 0x13
#define csCSDDONE 0x80 //Bit of CS_RST
#define csFSTTOOFAST 0x10 //Bit of CS_RST
#define csCSUNSTBL 0x08 //Bit of CS_RST
#define SYNCSTATUS 0x1f
#define SCHKRDY 0x80
#define VIPALIVE 0x08
#define SOGALIVE 0x04
#define HSALIVE 0x02
#define VSALIVE 0x01
/* Input capture register 0x00 - 0x2f */
#define FRM_STATUS 0x30
#define EXVSSH 0x20
#define ITLCPRO 0x02
#define SRC_SEL 0x31
#define IS_SPMD 0x20
#define IS_SEl 0x10
#define VIN_EN 0x08
#define EN_VSOFST 0x04
#define EN_HSOFST 0x02
#define INT_EDGE 0x01
#define ORG_FCNT 0x34
#define TM_1MS_L 0x35
#define TM_1MS_H 0x36
#define V_MISS_CNT 0x37
//#define H_MISS_CNT_L 0x38
//#define H_MISS_CNT_H 0x39
//#define VSYNC_DLT 0x3A
//#define HSYNC_DLT 0x3B
#define UDHSIZE_L 0x3C
#define UDHSIZE_H 0x3D
#define UDVSIZE_L 0x3E
#define UDVSZIE_H 0x3F
#define CAP_CTRL 0x67
#define INT_STATUS 0x32
#define ITLCFLG 0x40
#define INT_MASK 0x33
#define ATKACC 0x50
#define ATKACC_0 0x54
#define ATKACC_1 0x55
#define ATKACC_2 0x56
#define ATKACC_3 0x57
#define HS_PERIOD_L 0x58
#define HS_PERIOD_H 0x59
#define VS_PERIOD_L 0x5a
#define VS_PERIOD_H 0x5b
#define HS_WIDTH_L 0x5c
#define HS_WIDTH_H 0x5d
#define VS_WIDTH_L 0x5e
#define VS_WIDTH_H 0x5f
/* Auto Position Regs */
#define BOUNDCTR 0x26
#define THRESHOLD 0x27
#define POS_LB_L 0x28
#define POS_LB_H 0x29
#define POS_RB_L 0x2A
#define POS_RB_H 0x2B
#define POS_TB_L 0x2C
#define POS_TB_H 0x2D
#define POS_BB_L 0x2E
#define POS_BB_H 0x2F
#define HSYCOFS_L 0x41
#define HSYCOFS_H 0x42
#define VSYCOFS_L 0x43
#define VSYCOFS_H 0x44
#define HATVC_L 0x48
#define HATVC_H 0x49
#define VATVR_L 0x4A
#define VATVR_H 0x4B
#define HSST_L 0x4C
#define HSST_H 0x4D
#define VSST_L 0x4E
#define VSST_H 0x4F
/* Scaling Control */
#define DCLKI_IS_FASTER 0x10
#define INV_VIDEOF 0x20
#define SCALING_CTRL 0x70
#define COEF_DATA_PORT 0x71
#define SC_HOR_H1 0x72
#define SC_HOR_H2 0x73
#define SC_VER_V1 0x74
#define SC_VER_V2 0x75
/* Image Control */
#define IMG_FUN_CTRL 0x90
#define GAMMA_R 0xc0
#define GAMMA_G 0x80
#define GAMMA_B 0x40
#define GAMMA_RGB 0x00//0x3F
#define ENCONTRAST 0x10
#define ENBRIGHT 0x08
#define ENCSC 0x04
#define ENGAMMA 0x02
#define ENDITHER 0x01
#define PATTERN_CTRL 0x91
#define EFMCLR 0x80
#define DIGI_CONTRASTR 0x92
#define DIGI_CONTRASTG 0x93
#define DIGI_CONTRASTB 0x94
#define DIGI_BRIGHTR 0x96
#define DIGI_BRIGHTG 0x97
#define DIGI_BRIGHTB 0x98
#define YCoefCSC 0x97
#define CrCoef_R 0x98
#define CbCoef_G 0x99
#define CrCoef_G 0x9A
#define CbCoef_B 0x9B
#define GAMMA_ADDR 0x93
#define GAMMA_DATA 0x94
#define DITHERING 0x9C
/* OSD register definition */
#define OSD_CFG_INDEX 0xA0
#define OSD_CFG_DATA 0xA1
#define OSD_RAM_AL 0xA2
#define OSD_RAM_AH 0xA3
#define OSD_RAM_DL 0xA4
#define OSD_RAM_DH 0xA5
/* Output timing Control */
#define POUT_CTL_1 0xC0
#ifdef TCON
#define PSYNC_TCON_SW 0x08
#else
#define PSYNC_TCON_SW 0x00
#endif
#define POUT_CTL_3 0xC1
#define POUT_VSYNC_CTL 0xC2
#define PSYNC_STR 0x10
#define EN_SAVE_REC 0x04
#define IGNORE_VSYNC 0x02
#define PLLDIV_F 0xC8
#define PLLDIV_I 0xC9
#define PLLDIV_O 0xCA
#define PLLCFG_1 0xCB
#define PLLCFG_2 0xCC
/* Power Management */
#define POWER_REG 0xE0
#define PDADC_B 0x80
#define TPDB 0x40
#define PDMD 0x10
#define PDPLL_B 0x08
#define PDRX_B 0x04
#define PDC_B 0x02
#define PWDNTC 0x01
#define LVDS_CFG0 0xD0
#define BLH1 0xE2
#define BLH2 0xE3
#define BLH3 0xE4
#define BLL1 0xE5
#define BLL2 0xE6
#define BLL3 0xE7
#define BYPS_RX 0xFE
#define MAX_FONT 0x7B
#define FONT_RAM_START 0x00
#define WINDOW_RAM_START 0x07C0
#define LINE_WORD 0x20
#define X_SIZE 31
#define Y_SIZE 13
#define SUB_X_SIZE 31
#define MAIN_Y_SIZE 20
#define POS_Y_SIZE 9
#define IMAGE_Y_SIZE 14
#define X_OFFSET 0
#define Y_OFFSET 1
//#define BLACK_WHITE 0x2f
#define BLACK_BLUE 0x21
#define BLACK_PW_BLUE 0x23
#define BLACK_ORANGE 0x24
#define BLACK_GREEN 0x25
#define BLACK_L_GRAY 0x26
#define BLACK_OLIVE 0x27
#define BLACK_D_GRAY 0x28
#define BLACK_RED 0x29
#define BLACK_PURPLE 0x2A
#define TITLE_ATTR 0x62
#define GRAY_ORANGE 0x64
#define GRAY_PW_BLUE 0x63
#define HEADER_ATTR 0x2e
#define GRAY_D_GRAY 0x68
#define TRANSPARENT 0x00
#define ROW_ATTR 0x00 //80
#define HIGHLIGHT_ATTR 0xA0 //c0
/* PanelLink Reciever */
#define RXCFG0 0x20
#define RXCFG1 0x21
#define RXCFG2 0x22
#define RXCFG3 0x23
#define RXCFG4 0x24
#define RXCFG5 0x25
#define RXCFG6 0x26
#define RXCFG7 0x27
#define RXCFG8 0x28
#define RXCFG9 0x29
#define RXCFGA 0x2A
#define RXCFGB 0x2B
/* Two Wire Bus Slave Interface */
#define TW_INTERFACE 0xF1
#define AUTO_INC 0x04
#define TWO_BUS 0x00
#define TWO_FOUR_BUS 0x01
#define TWO_DDC_BUS 0x02
#define TWO_BVSI_BUS 0x03
#define DID_L 0xf6
/* bit definition */
//#define I2C_FORCE_SEL 0x40
#define TW_FORCE_SEL 0x40
#define IS_SPMD 0x20
#define IS_SEL 0x10
#define HSYNC_POLARITY 0x02
#define VSYNC_POLARITY 0x01
#define LE_VSYNC 0x20
#define TIME_OUT 0x10
#define HSYNC_CHANGE 0x08
#define VSYNC_CHANGE 0x04
#define HSYNC_MISS 0x02
#define VSYNC_MISS 0x01
/* not used
#define ATKR 0x02
#define ATKE 0x01
*/
#define SHARPNESS_ON 0x20
#define SHARPNESS_OFF 0xdf
#define CONTRA_ON 0x10
#define CONTRA_OFF 0xef
#define BRIGHT_ON 0x08
#define BRIGHT_OFF 0xf7
#define GAMMAIOTAB_ON 0x04
#define GAMMAIOTAB_OFF 0xfb
#define GAMMA_OFF 0xfd
#define DITHERING_ON 0x01
#define DITHERING_OFF 0xfe
#endif //__TW803_REGS_H__
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