📄 bpsk_sim.mdl
字号:
Model {
Name "BPSK_sim"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Mon Sep 24 09:12:04 2007"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "阮慧萍"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Mon Sep 24 09:31:42 2007"
ModelVersionFormat "1.%<AutoIncrement:3>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType FrameConversion
OutFrame "Frame-based"
}
Block {
BlockType Ground
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Rounding
Operator "floor"
}
Block {
BlockType Selector
InputType "Vector"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "BPSK_sim"
Location [216, 236, 1018, 529]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel"
Ports [1, 1]
Position [275, 29, 355, 71]
FontSize 10
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
seed "67"
noiseMode "Signal to noise ratio (SNR)"
EsNodB "10"
SNRdB "SNR"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Reference
Name "Error Rate\nCalculation"
Ports [2, 1]
Position [495, 37, 570, 88]
FontSize 10
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop off
numErr "100"
maxBits "1e6"
}
Block {
BlockType Reference
Name "M-FSK\nDemodulator\nBaseband"
Ports [1, 1]
Position [385, 26, 460, 74]
FontSize 10
SourceBlock "commdigbbndfm2/M-FSK\nDemodulator\nBaseband"
SourceType "M-FSK Demodulator Baseband"
M "2"
OutType "Bit"
Dec "Gray"
freqSep "FrequencySeparation"
numSamp "SamplesPerSymbol"
}
Block {
BlockType Reference
Name "M-FSK\nModulator\nBaseband"
Ports [1, 1]
Position [155, 25, 230, 75]
FontSize 10
SourceBlock "commdigbbndfm2/M-FSK\nModulator\nBaseband"
SourceType "M-FSK Modulator Baseband"
M "2"
InType "Bit"
Enc "Gray"
freqSep "FrequencySeparation"
phaseType "Continuous"
numSamp "SamplesPerSymbol"
}
Block {
BlockType Reference
Name "Random Integer\nGenerator"
Ports [0, 1]
Position [35, 28, 115, 72]
FontName "Arial"
FontSize 10
SourceBlock "commrandsrc2/Random Integer\nGenerator"
SourceType "Random Integer Generator"
mul "2"
seed "37"
Ts "1/(2*BitRate)"
frameBased on
sampPerFrame "2*BitRate"
orient off
}
Block {
BlockType Selector
Name "Selector"
Ports [1, 1]
Position [610, 46, 650, 84]
InputPortWidth "3"
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [690, 50, 750, 80]
VariableName "BitErrorRate"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Line {
SrcBlock "Random Integer\nGenerator"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "M-FSK\nModulator\nBaseband"
DstPort 1
}
Branch {
Points [0, 65; 350, 0]
DstBlock "Error Rate\nCalculation"
DstPort 2
}
}
Line {
SrcBlock "M-FSK\nModulator\nBaseband"
SrcPort 1
DstBlock "AWGN\nChannel"
DstPort 1
}
Line {
SrcBlock "AWGN\nChannel"
SrcPort 1
DstBlock "M-FSK\nDemodulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "M-FSK\nDemodulator\nBaseband"
SrcPort 1
DstBlock "Error Rate\nCalculation"
DstPort 1
}
Line {
SrcBlock "Error Rate\nCalculation"
SrcPort 1
DstBlock "Selector"
DstPort 1
}
Line {
SrcBlock "Selector"
SrcPort 1
DstBlock "To Workspace"
DstPort 1
}
}
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -