📄 tvptc_fw.h
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#ifndef TVPTC_FW_DOT_H_IS_DEFINED
#define TVPTC_FW_DOT_H_IS_DEFINED
/*****************************************************************************
* Property of Texas Instruments Incorporated, Copyright 2004
* All rights reserved
******************************************************************************/
/*********************************************************************
*
* Description:
* TvpTc_fw.h contains all private global defines for the Traffic Controller.
*
*
**********************************************************************/
/*********************************************************************
*
* $Revision: $
*
* $History: TvpTc_fw.h $
*
*********************************************************************/
// tc hardware register definitons
// (see TvpInt.h for irq interrupt registers)
// made public for independant OS implementation
#define TVP_FIQ_REQ (TVP_SYS_CONFIG_BASE+0x0) // Pending FIQ requests
#define TVP_FIQ_MASK (TVP_SYS_CONFIG_BASE+0x2) // Bitwise-mask of FIQ requests
#define TVP_FIQ_STATUS (TVP_SYS_CONFIG_BASE+0x4) // Result of applying FIQ_MASK to FIQ_REQ
#define TVP_FIQ_SRC (TVP_SYS_CONFIG_BASE+0x6) // Specifies the highest priority FIQ active in FIQ_STATUS
#define TVP_FIQ_MASK_ALL (TVP_SYS_CONFIG_BASE+0x7) // Mask all FIQ requests
#define TVP_FIQ_PRI0 (TVP_SYS_CONFIG_BASE+0x40) // Priority for FIQ request bit 0
#define TVP_FIQ_PRI1 (TVP_SYS_CONFIG_BASE+0x41) // Priority for FIQ request bit 1
#define TVP_FIQ_PRI2 (TVP_SYS_CONFIG_BASE+0x42) // Priority for FIQ request bit 2
#define TVP_FIQ_PRI3 (TVP_SYS_CONFIG_BASE+0x43) // Priority for FIQ request bit 3
#define TVP_FIQ_PRI4 (TVP_SYS_CONFIG_BASE+0x44) // Priority for FIQ request bit 4
#define TVP_FIQ_PRI5 (TVP_SYS_CONFIG_BASE+0x45) // Priority for FIQ request bit 5
#define TVP_FIQ_PRI6 (TVP_SYS_CONFIG_BASE+0x46) // Priority for FIQ request bit 6
#define TVP_FIQ_PRI7 (TVP_SYS_CONFIG_BASE+0x47) // Priority for FIQ request bit 7
#define TVP_FIQ_PRI8 (TVP_SYS_CONFIG_BASE+0x48) // Priority for FIQ request bit 8
#define TVP_FIQ_PRI9 (TVP_SYS_CONFIG_BASE+0x49) // Priority for FIQ request bit 9
#define TVP_FIQ_PRIA (TVP_SYS_CONFIG_BASE+0x4a) // Priority for FIQ request bit a
#define TVP_FIQ_PRIB (TVP_SYS_CONFIG_BASE+0x4b) // Priority for FIQ request bit b
#define TVP_FIQ_PRIC (TVP_SYS_CONFIG_BASE+0x4c) // Priority for FIQ request bit c
#define TVP_FIQ_PRID (TVP_SYS_CONFIG_BASE+0x4d) // Priority for FIQ request bit d
#define TVP_FIQ_PRIE (TVP_SYS_CONFIG_BASE+0x4e) // Priority for FIQ request bit e
#define TVP_FIQ_PRIF (TVP_SYS_CONFIG_BASE+0x4f) // Priority for FIQ request bit f
#define TVP_FIQ_PRI10 (TVP_SYS_CONFIG_BASE+0x50) // Priority for FIQ request bit 10
#define TVP_FIQ_PRI11 (TVP_SYS_CONFIG_BASE+0x51) // Priority for FIQ request bit 11
#define TVP_FIQ_PRI12 (TVP_SYS_CONFIG_BASE+0x52) // Priority for FIQ request bit 12
#define TVP_FIQ_PRI13 (TVP_SYS_CONFIG_BASE+0x53) // Priority for FIQ request bit 13
#define TVP_FIQ_PRI14 (TVP_SYS_CONFIG_BASE+0x54) // Priority for FIQ request bit 14
#define TVP_FIQ_PRI15 (TVP_SYS_CONFIG_BASE+0x55) // Priority for FIQ request bit 15
#define TVP_FIQ_PRI16 (TVP_SYS_CONFIG_BASE+0x56) // Priority for FIQ request bit 16
#define TVP_FIQ_PRI17 (TVP_SYS_CONFIG_BASE+0x57) // Priority for FIQ request bit 17
#define TVP_FIQ_PRI18 (TVP_SYS_CONFIG_BASE+0x58) // Priority for FIQ request bit 18
#define TVP_FIQ_PRI19 (TVP_SYS_CONFIG_BASE+0x59) // Priority for FIQ request bit 19
#define TVP_FIQ_PRI1A (TVP_SYS_CONFIG_BASE+0x5a) // Priority for FIQ request bit 1a
#define TVP_FIQ_PRI1B (TVP_SYS_CONFIG_BASE+0x5b) // Priority for FIQ request bit 1b
#define TVP_FIQ_PRI1C (TVP_SYS_CONFIG_BASE+0x5c) // Priority for FIQ request bit 1c
#define TVP_FIQ_PRI1D (TVP_SYS_CONFIG_BASE+0x5d) // Priority for FIQ request bit 1d
#define TVP_FIQ_PRI1E (TVP_SYS_CONFIG_BASE+0x5e) // Priority for FIQ request bit 1e
#define TVP_FIQ_PRI1F (TVP_SYS_CONFIG_BASE+0x5f) // Priority for FIQ request bit 1f
#define TVP_IRQ_PRI0 (TVP_SYS_CONFIG_BASE+0x80) // Priority for IRQ request bit 0
#define TVP_IRQ_PRI1 (TVP_SYS_CONFIG_BASE+0x81) // Priority for IRQ request bit 1
#define TVP_IRQ_PRI2 (TVP_SYS_CONFIG_BASE+0x82) // Priority for IRQ request bit 2
#define TVP_IRQ_PRI3 (TVP_SYS_CONFIG_BASE+0x83) // Priority for IRQ request bit 3
#define TVP_IRQ_PRI4 (TVP_SYS_CONFIG_BASE+0x84) // Priority for IRQ request bit 4
#define TVP_IRQ_PRI5 (TVP_SYS_CONFIG_BASE+0x85) // Priority for IRQ request bit 5
#define TVP_IRQ_PRI6 (TVP_SYS_CONFIG_BASE+0x86) // Priority for IRQ request bit 6
#define TVP_IRQ_PRI7 (TVP_SYS_CONFIG_BASE+0x87) // Priority for IRQ request bit 7
#define TVP_IRQ_PRI8 (TVP_SYS_CONFIG_BASE+0x88) // Priority for IRQ request bit 8
#define TVP_IRQ_PRI9 (TVP_SYS_CONFIG_BASE+0x89) // Priority for IRQ request bit 9
#define TVP_IRQ_PRIA (TVP_SYS_CONFIG_BASE+0x8a) // Priority for IRQ request bit a
#define TVP_IRQ_PRIB (TVP_SYS_CONFIG_BASE+0x8b) // Priority for IRQ request bit b
#define TVP_IRQ_PRIC (TVP_SYS_CONFIG_BASE+0x8c) // Priority for IRQ request bit c
#define TVP_IRQ_PRID (TVP_SYS_CONFIG_BASE+0x8d) // Priority for IRQ request bit d
#define TVP_IRQ_PRIE (TVP_SYS_CONFIG_BASE+0x8e) // Priority for IRQ request bit e
#define TVP_IRQ_PRIF (TVP_SYS_CONFIG_BASE+0x8f) // Priority for IRQ request bit f
#define TVP_IRQ_PRI10 (TVP_SYS_CONFIG_BASE+0x90) // Priority for IRQ request bit 10
#define TVP_IRQ_PRI11 (TVP_SYS_CONFIG_BASE+0x91) // Priority for IRQ request bit 11
#define TVP_IRQ_PRI12 (TVP_SYS_CONFIG_BASE+0x92) // Priority for IRQ request bit 12
#define TVP_IRQ_PRI13 (TVP_SYS_CONFIG_BASE+0x93) // Priority for IRQ request bit 13
#define TVP_IRQ_PRI14 (TVP_SYS_CONFIG_BASE+0x94) // Priority for IRQ request bit 14
#define TVP_IRQ_PRI15 (TVP_SYS_CONFIG_BASE+0x95) // Priority for IRQ request bit 15
#define TVP_IRQ_PRI16 (TVP_SYS_CONFIG_BASE+0x96) // Priority for IRQ request bit 16
#define TVP_IRQ_PRI17 (TVP_SYS_CONFIG_BASE+0x97) // Priority for IRQ request bit 17
#define TVP_IRQ_PRI18 (TVP_SYS_CONFIG_BASE+0x98) // Priority for IRQ request bit 18
#define TVP_IRQ_PRI19 (TVP_SYS_CONFIG_BASE+0x99) // Priority for IRQ request bit 19
#define TVP_IRQ_PRI1A (TVP_SYS_CONFIG_BASE+0x9a) // Priority for IRQ request bit 1a
#define TVP_IRQ_PRI1B (TVP_SYS_CONFIG_BASE+0x9b) // Priority for IRQ request bit 1b
#define TVP_IRQ_PRI1C (TVP_SYS_CONFIG_BASE+0x9c) // Priority for IRQ request bit 1c
#define TVP_IRQ_PRI1D (TVP_SYS_CONFIG_BASE+0x9d) // Priority for IRQ request bit 1d
#define TVP_IRQ_PRI1E (TVP_SYS_CONFIG_BASE+0x9e) // Priority for IRQ request bit 1e
#define TVP_IRQ_PRI1F (TVP_SYS_CONFIG_BASE+0x9f) // Priority for IRQ request bit 1f
#define TVP_FIQ_REQ_SET (TVP_SYS_CONFIG_BASE+0xc0) // Bitwise-set for FIQ_REQ register
#define TVP_FIQ_REQ_CLR (TVP_SYS_CONFIG_BASE+0xc2) // Bitwise-clear for FIQ_REQ register
#define TVP_SYS_CFG0 (TVP_SYS_CONFIG_BASE+0x200) // 0x00020800
#define TVP_SYS_CFG1 (TVP_SYS_CONFIG_BASE+0x201) // 0x00020804
#define TVP_SYS_CFG2 (TVP_SYS_CONFIG_BASE+0x202) // 0x00020808
#define TVP_SYS_SUNDIAL_CFG (TVP_SYS_CONFIG_BASE+0x203) // 0x0002080c
#define TVP_SYS_MON0 (TVP_SYS_CONFIG_BASE+0x204) // 0x00020810
#define TVP_SYS_MON1 (TVP_SYS_CONFIG_BASE+0x205) // 0x00020814
#define TVP_SYS_MON2 (TVP_SYS_CONFIG_BASE+0x206) // 0x00020818
#define TVP_SYS_HI_ERROR_STS (TVP_SYS_CONFIG_BASE+0x207) // 0x0002081c
#define TVP_SYS_SWRST_SET (TVP_SYS_CONFIG_BASE+0x208) // 0x00020820
#define TVP_SYS_SWRST_CLR (TVP_SYS_CONFIG_BASE+0x209) // 0x00020824
#define TVP_SYS_SWRST_CFG (TVP_SYS_CONFIG_BASE+0x20a) // 0x00020828
#define TVP_SYS_SWRST_STS (TVP_SYS_CONFIG_BASE+0x20b) // 0x0002082c
#define TVP_EXT_CS0_CFG0 (TVP_EBI_CONFIG_BASE+0x0) // Configuration for chip select 0
#define TVP_EXT_CS0_CFG1 (TVP_EBI_CONFIG_BASE+0x1) // Configuration for chip select 0
#define TVP_EXT_CS0_CFG2 (TVP_EBI_CONFIG_BASE+0x2) // Configuration for chip select 0
#define TVP_EXT_CS0_CFG3 (TVP_EBI_CONFIG_BASE+0x3) // Configuration for chip select 0
#define TVP_EXT_CS0_CFG4 (TVP_EBI_CONFIG_BASE+0x4) // Configuration for chip select 0
#define TVP_EXT_CS1_CFG0 (TVP_EBI_CONFIG_BASE+0x8) // Configuration for chip select 1
#define TVP_EXT_CS1_CFG1 (TVP_EBI_CONFIG_BASE+0x9) // Configuration for chip select 1
#define TVP_EXT_CS1_CFG2 (TVP_EBI_CONFIG_BASE+0xa) // Configuration for chip select 1
#define TVP_EXT_CS1_CFG3 (TVP_EBI_CONFIG_BASE+0xb) // Configuration for chip select 1
#define TVP_EXT_CS1_CFG4 (TVP_EBI_CONFIG_BASE+0xc) // Configuration for chip select 1
#define TVP_EXT_CS2_CFG0 (TVP_EBI_CONFIG_BASE+0x10) // Configuration for chip select 2
#define TVP_EXT_CS2_CFG1 (TVP_EBI_CONFIG_BASE+0x11) // Configuration for chip select 2
#define TVP_EXT_CS2_CFG2 (TVP_EBI_CONFIG_BASE+0x12) // Configuration for chip select 2
#define TVP_EXT_CS2_CFG3 (TVP_EBI_CONFIG_BASE+0x13) // Configuration for chip select 2
#define TVP_EXT_CS2_CFG4 (TVP_EBI_CONFIG_BASE+0x14) // Configuration for chip select 2
#define TVP_EXT_CS3_CFG0 (TVP_EBI_CONFIG_BASE+0x18) // Configuration for chip select 3
#define TVP_EXT_CS3_CFG1 (TVP_EBI_CONFIG_BASE+0x19) // Configuration for chip select 3
#define TVP_EXT_CS3_CFG2 (TVP_EBI_CONFIG_BASE+0x1a) // Configuration for chip select 3
#define TVP_EXT_CS3_CFG3 (TVP_EBI_CONFIG_BASE+0x1b) // Configuration for chip select 3
#define TVP_EXT_CS3_CFG4 (TVP_EBI_CONFIG_BASE+0x1c) // Configuration for chip select 3
#define TVP_EXT_CS4_CFG0 (TVP_EBI_CONFIG_BASE+0x20) // Configuration for chip select 4
#define TVP_EXT_CS4_CFG1 (TVP_EBI_CONFIG_BASE+0x21) // Configuration for chip select 4
#define TVP_EXT_CS4_CFG2 (TVP_EBI_CONFIG_BASE+0x22) // Configuration for chip select 4
#define TVP_EXT_CS4_CFG3 (TVP_EBI_CONFIG_BASE+0x23) // Configuration for chip select 4
#define TVP_EXT_CS4_CFG4 (TVP_EBI_CONFIG_BASE+0x24) // Configuration for chip select 4
#define TVP_EXT_CS5_CFG0 (TVP_EBI_CONFIG_BASE+0x28) // Configuration for chip select 5
#define TVP_EXT_CS5_CFG1 (TVP_EBI_CONFIG_BASE+0x29) // Configuration for chip select 5
#define TVP_EXT_CS5_CFG2 (TVP_EBI_CONFIG_BASE+0x2a) // Configuration for chip select 5
#define TVP_EXT_CS5_CFG3 (TVP_EBI_CONFIG_BASE+0x2b) // Configuration for chip select 5
#define TVP_EXT_CS5_CFG4 (TVP_EBI_CONFIG_BASE+0x2c) // Configuration for chip select 5
#define TVP_EXT_INT_CFG (TVP_EBI_CONFIG_BASE+0x30) // Configuration for external interrupts
#define TVP_EXT_WAIT_ERR (TVP_EBI_CONFIG_BASE+0x31) // Holds EXT_WAIT error information
#define TVP_EXT_WAIT_TO (TVP_EBI_CONFIG_BASE+0x33) // EXT_WAIT_TIMEOUT
/*--------------------------**
** SYS_MON2 Bit Definitions **
**--------------------------*/
#define TVP_SYS_DDR32_CFG 0x1
/*--------------------------**
** SYS_CFG2 Bit Definitions **
**--------------------------*/
#define TVP_DVO_INVERT 0x80000000
/*----------------------------------------------**
** TVP_SYS_SUNDIAL_CFG Register Bit Definitions **
**----------------------------------------------*/
#define TVP_SYS_SCFG_READ_CLR 0
#define TVP_SYS_SCFG_WRITE_1_CLR 2
#define TVP_SYS_SCFG_WRITE_0_CLR 6
#define TVP_SYS_SCFG_STAT_ENABLE 1
#endif
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