tvpsmrtcard_fw.h

ti的数字电视芯片 tvp9000的源码

#ifndef  TVP_SMRT_CARD_FW_DOT_H_IS_DEFINED
#define  TVP_SMRT_CARD_FW_DOT_H_IS_DEFINED

/********************************************************************* 
*    Property of Texas Instruments Incorporated, Copyright 2004
*    All rights reserved
**********************************************************************/
/*********************************************************************
*
* Description:
*   private include file for smart card modules
*   It includes the definitions that are not needed for the API:
*   an application program must not include this file.
*   
**********************************************************************/
/*********************************************************************
*
* $Revision: $
*
* $History: TvpSmrtCard_fw.h $
* 
*********************************************************************
* NOTE
* BIG NOTE!!!! There is a bug in the hardware. The CRC_RXCRC bit is intended as
* bit 16 (0x10000). Due to a hardware bug, it is located in bit 16 for reads only!!
* For writes, it is located in bit 9 (0x100). There are no plans to fix this simple
* problem in hardware, so the software must write to bit 9 (0x100) to set/clear the
* rxcrc control. If you want to read the status, read bit 16!
* 
* Side note - Please be very careful when writing to this entire register. This 
* especially is true for read-modify-write operations!
*********************************************************************/

/* Common Constants */
#define TVP_CMD_HDR_COMP        5       // Command Header complete byte count   
#define TVP_SMRT_CALLBACK        0xff

/* Memory map - These are all word offsets from the base 
   smart card address. The offsets are also maintained and used
   as a structure, but are presented here for completeness and
   doceumentation purposes. */
#define TVP_SMRT_URB_OFFSET      0
#define TVP_SMRT_UTB_OFFSET      0
#define TVP_SMRT_SCCC_OFFSET     1
#define TVP_SMRT_SCS_OFFSET      2
#define TVP_SMRT_SCIC_OFFSET     3
#define TVP_SMRT_BITDIV_OFFSET   4
#define TVP_SMRT_VCCDET_OFFSET   5
#define TVP_SMRT_WWTIM_OFFSET    6
#define TVP_SMRT_RXEDC_OFFSET    7
#define TVP_SMRT_BWT_OFFSET      8
#define TVP_SMRT_FTO_OFFSET      9
#define TVP_SMRT_SCIM_OFFSET    10
#define TVP_SMRT_SCIS_OFFSET    11
#define TVP_SMRT_SCRC_OFFSET    12
#define TVP_SMRT_TXEDC_OFFSET   13
#define TVP_SMRT_SBITDIV_OFFSET 14


/* Register Bit Masks */

/* SCCC (Smart Card UART Communication Control Register */
#define TVP_VCCDET          0x400000    // SMCVccDetect Input Pin 1=Used  0=Not Used
#define TVP_SCTRANS         0x200000    // ATR and optional PTS sequence(s) complete
#define TVP_ODXFER          0x100000    // Outgoing T=0 data transfer (Card to IFD) 
#define TVP_HW_VPPEN        0x80000     // Vpp enable/disable under hardware control
#define TVP_PEN             0x40000     // Parity Generation and Checking Enabled   
#define TVP_FIL_CLEAR       0x30000     // Fifo Interrupt Level 0=Half 1=1/4        
#define TVP_FIL_QUART       0x00000
#define TVP_FIL_HALF        0x10000
#define TVP_FIL_3_QUART     0x20000
#define TVP_GDTIM_HW_CLEAR  0xff00
#define TVP_GDTIM_HW_SHIFT  8
#define TVP_INIT_GDTIM      (2 << TVP_GDTIM_HW_SHIFT)
#define TVP_NNAK_CLEAR      0xf0
#define TVP_NNAK_SHIFT      4
#define TVP_NPER_CLEAR      0xf

#define TVP_INIT_FIFO_LEVEL TVP_FIL_HALF
/* SCS (Smart Card UART Status Register) bit masks */

#define TVP_CRD_TYPE        0x800000    // Card Type 1=Internal Reset, 0=Active Low     
#define TVP_EDCSTAT         0x400000    // Error Detection Code Status                  
#define TVP_RX_TX           0x200000    // RX/RX Status on turn-arounds                 
#define TVP_SMVCC           0x100000    // VCC Detect                                   
#define TVP_RX_VALUE        0x80000     // Value of SMIO line when contacts are active  
#define TVP_TX_ENZ          0x40000     // Identifies who is driving I/O line 1=card    
#define TVP_ICC             0x20000     // Convention : Direct (0) or Inverse (1)       
#define TVP_SSTAT           0x10000     // Smart Card status 1=installed 0=removed      
#define TVP_TXFCNT_MASK     0x1f00
#define TVP_TXFCNT_SHIFT    8
#define TVP_RFCNT_MASK      0x1f    // Receive Fifo Count                           


/* Smart Card Interrupt Status Register  bit masks                  */
#define TVP_SMRT_SCIS_NOT_USED  1       // Number of status bits not used           
#define TVP_SMRT_SCIS_NU_MASK   0x8000  // Mask of not used bits

#define TVP_DR                  0x4000  // Data ready                               
#define TVP_FTOSTAT             0x2000  // Receive Fifo Time Out                    
#define TVP_OE                  0x1000  // Overrun Error                            
#define TVP_TXFHF               0x0800  // Transmitter fifo half full               
#define TVP_THRE                0x0400  // Transmitter holding register empty       
#define TVP_RXFHF               0x0200  // Receive fifo half full                   
#define TVP_BWTE                0x0100  // Work Wait Time Error                     
#define TVP_WWTE                0x0080  // Work Wait Time Error                     
#define TVP_ICOM                0x0040  // Initialization complete                  
#define TVP_CLK_STOPPED         0x0020  // Smart Card Detect                        
#define TVP_SMDE                0x0010  // Smart Card Detect                        
#define TVP_VCCDE               0x0008  // VCC Detect                               
#define TVP_NO_ATR              0x0004  // Answer to Reset never occurred           
#define TVP_NAK                 0x0002  // NAK error                                
#define TVP_PE                  0x0001  // Parity error                             

#define TVP_SMRT_CLEAR_ALL   0x3fff  // Write a one to all int. bits except DR       */

/* SCIC (Smart Card Interface Control Register) bit masks */
#define TVP_TDA_CLKDIV_OUT  0x800000    // TDA8004 mode: Bring out CLKDIV1&2 for outputs
#define TVP_TDA8004         0x400000    // TDA8004 chip in use 
#define TVP_SCVOEN          0x200000    // Voltage Output enable for VCCEN and VPP  
#define TVP_WTRO            0x100000    // Wait Time Roll Over
#define TVP_TXDRV1          0x80000     // Transmitter Drive 1 (open collector)
#define TVP_NAKCNTL_MASK    0x60000     // Test mode NAK Control
#define TVP_NAK_ONE_IRQ     0           // Test mode only
#define TVP_NAK_ONE_RESEND  0x20000     // Test mode only
#define TVP_NAK_ONE_FLUSH   0x40000     // Test mode only
#define TVP_NAK_MULT_RETRY  0x60000     // Test mode only
#define TVP_FLIPP           0x10000     // Flip Parity (Test Mode only)
#define TVP_TMODE           0x8000      // Test Mode
#define TVP_SCVPPENP        0x4000      // Active polarity for Vpp
#define TVP_SCVCCENP        0x2000      // Active polarity for Vcc
#define TVP_VPPEN           0x1000      // VPP enable
#define TVP_VCCEN           0x800       // VCC enable
#define TVP_EDC_F           0x400       // EDC Type 0=LRC 1=CRC
#define TVP_PTS             0x200       // Protocol Type  0 T=0 / 1 T=1 
#define TVP_FC              0x100       // Flow Control 0=Disable/1=Enable 
#define TVP_SC_RST          0x80        // Reset signal (1=reset)
#define TVP_SCDL            0x40        // Smart Card Detect Level  1=IN    
#define TVP_STOP_CLK        0x20        // Stop Clock control (1=stop)
#define TVP_CLK_STATE       0x10        // Value of clock in stop state (0 or 1)
#define TVP_SMRT_CLEAR_CLOCK 0xf         // Clear the old clock select value


/* SCIM (Smart Card Interrupt Mask Register) bit masks   */
#define TVP_DRM         0x100       // Data Ready Mask                      
#define TVP_FTOM        0x80        // Fifo Time Out Mask                   
#define TVP_TXRX_FIFOM  0x40        // Tx/Rcv Half Full Interupt Mask       
#define TVP_THREM       0x20        // Tx Holding Register Empty Mask       
#define TVP_BWTM        0x10        // Block Wait Time interrupt Mask       
#define TVP_WWTM        0x8         // Work Wait Time interrupt Mask        
#define TVP_ICOMM       0x4         // Initialization Complete Mask         
#define TVP_CLK_STOPM   0x2         // Clock Stop mask
#define TVP_SMDETM      0x1         // Smart Card Detect Mask
                                         
#define TVP_SMRT_MASK_ALL                0x1ff   // Enables all masks   
#define TVP_SMRT_MASK_ALL_EXCEPT_SMDETM  0x1fe

#define TVP_MAX_FIFO_SIZE   16      // Size of Tx and Rcv Fifo in bytes 
#define TVP_MAX_FIFO_DEPTH_COUNT 12
#define TVP_MAX_PPS_SIZE    TVP_MAX_FIFO_SIZE
#define TVP_SEND_EDC        0       // Send the hardware generated EDC character    
#define TVP_SEND_NO_EDC     1


/* SCRC (Smart Card CRC Register) definitions   */

/*-----------------------------------------------------------------------------------**
** BIG NOTE!!!! There is a bug in the hardware. The CRC_RXCRC bit is intended as     **
** bit 16 (0x10000). Due to a hardware bug, it is located in bit 16 for reads only!! **
** For writes, it is located in bit 9 (0x100). There are no plans to fix this simple **
** problem in hardware, so the software must write to bit 9 (0x100) to set/clear the **
** rxcrc control. If you want to read the status, read bit 16!                       **
**                                                                                   **
** Side note - Please be very careful when writing to this entire register. This     **
** especially is true for read-modify-write operations!                              **
**-----------------------------------------------------------------------------------*/