tvposdmem.h

ti的数字电视芯片 tvp9000的源码

#ifndef TVP_OSD_MEM_DOT_H_IS_DEFINED
#define TVP_OSD_MEM_DOT_H_IS_DEFINED

/********************************************************************* 
*    Property of Texas Instruments Incorporated, Copyright 2004
*    All rights reserved
**********************************************************************/
/*********************************************************************
*
* Description:
*   H/W registers/memory for the OSD module
*
*   
**********************************************************************/
/*********************************************************************
*
* $Revision: $
*
* $History: TvpOsdMem.h $
* 
*********************************************************************/

// OSD Configuration / Status Registers
#define TVP_OSD_CFG                 ((volatile unsigned long *)(TVP_OSD_BASE + 0x0))
#define TVP_OSD_DISP_W              ((volatile unsigned long *)(TVP_OSD_BASE + 0x1))
#define TVP_OSD_DISP_H              ((volatile unsigned long *)(TVP_OSD_BASE + 0x2))
#define TVP_OSD_GPU_RP_SWITCH_EN    ((volatile unsigned long *)(TVP_OSD_BASE + 0x3))
#define TVP_OSD_DISP_OUT_CFG        ((volatile unsigned long *)(TVP_OSD_BASE + 0x4))
#define TVP_OSD_NTSC_OUT_CFG        ((volatile unsigned long *)(TVP_OSD_BASE + 0x5))
#define TVP_OSD_CFG_LOAD_EN         ((volatile unsigned long *)(TVP_OSD_BASE + 0x6))

// OSD Graphics Layer Configuration                                                 
#define TVP_OSD_GPU_ENABLE          ((volatile unsigned long *)(TVP_OSD_BASE + 0x10))
#define TVP_OSD_GPU_ATTR_BA0_INIT   ((volatile unsigned long *)(TVP_OSD_BASE + 0x11))
#define TVP_OSD_GPU_ATTR_BA1_INIT   ((volatile unsigned long *)(TVP_OSD_BASE + 0x12))

// OSD Video Layer Configuration
#define TVP_OSD_VID_ENABLE          ((volatile unsigned long *)(TVP_OSD_BASE + 0x20))
#define TVP_OSD_VID_CFG             ((volatile unsigned long *)(TVP_OSD_BASE + 0x21))
#define TVP_OSD_VID_XY              ((volatile unsigned long *)(TVP_OSD_BASE + 0x22))
#define TVP_OSD_VID_WH              ((volatile unsigned long *)(TVP_OSD_BASE + 0x23))
#define TVP_OSD_VID_TRANS_CFG       ((volatile unsigned long *)(TVP_OSD_BASE + 0x24))

// OSD Still Layer Configuration
#define TVP_OSD_STL_ENABLE          ((volatile unsigned long *)(TVP_OSD_BASE + 0x30))
#define TVP_OSD_STL_CFG             ((volatile unsigned long *)(TVP_OSD_BASE + 0x31))
#define TVP_OSD_STL_XY              ((volatile unsigned long *)(TVP_OSD_BASE + 0x32))
#define TVP_OSD_STL_WH              ((volatile unsigned long *)(TVP_OSD_BASE + 0x33))
#define TVP_OSD_STL_SRC_BA          ((volatile unsigned long *)(TVP_OSD_BASE + 0x34))
#define TVP_OSD_STL_SRC_LS          ((volatile unsigned long *)(TVP_OSD_BASE + 0x35))
#define TVP_OSD_STL_TRANS_CFG       ((volatile unsigned long *)(TVP_OSD_BASE + 0x36))

// OSD Cursor Layer Configuration
#define TVP_OSD_CUR_ENABLE          ((volatile unsigned long *)(TVP_OSD_BASE + 0x40))
#define TVP_OSD_CUR_CFG             ((volatile unsigned long *)(TVP_OSD_BASE + 0x41))
#define TVP_OSD_CUR_XY              ((volatile unsigned long *)(TVP_OSD_BASE + 0x42))
#define TVP_OSD_CUR_WH              ((volatile unsigned long *)(TVP_OSD_BASE + 0x43))
#define TVP_OSD_CUR_SRC_BA          ((volatile unsigned long *)(TVP_OSD_BASE + 0x44))
#define TVP_OSD_CUR_COLOR_0         ((volatile unsigned long *)(TVP_OSD_BASE + 0x45))
#define TVP_OSD_CUR_COLOR_1         ((volatile unsigned long *)(TVP_OSD_BASE + 0x46))
#define TVP_OSD_CUR_COLOR_2         ((volatile unsigned long *)(TVP_OSD_BASE + 0x47))
#define TVP_OSD_CUR_COLOR_3         ((volatile unsigned long *)(TVP_OSD_BASE + 0x48))

// OSD_GPU Layer Configuration
#define TVP_OSD_GPU0_ENABLE         0x1
#define TVP_OSD_GPU1_ENABLE         0x2
#define TVP_OSD_AF_ENABLE           0x4


// OSD Background Layer Configuration
#define TVP_OSD_BG_COLOR            (volatile unsigned long *)(TVP_OSD_BASE + 0x50)

// OSD Switch Control Layer Configuration
#define TVP_OSD_SWP_ENABLE          (volatile unsigned long *)(TVP_OSD_BASE + 0x60)
#define TVP_OSD_SWP_BA_INIT         (volatile unsigned long *)(TVP_OSD_BASE + 0x61)

// OSD Position defines
#define TVP_OSD_X_POS_MASK          0x7ff
#define TVP_OSD_X_POS_SHIFT         11
#define TVP_OSD_Y_POS_MASK          0x7ff
#define TVP_OSD_Y_POS_SHIFT         0

#define TVP_OSD_W_MASK              0x7ff
#define TVP_OSD_W_SHIFT             11
#define TVP_OSD_H_MASK              0x7ff
#define TVP_OSD_H_SHIFT             0

#define TVP_OSD_TRANS_OFF_MASK      0x07000000
#define TVP_OSD_TRANS_ON            0x06000000

#define TVP_OSD_LAYER_ENABLE        1
#define TVP_OSD_LAYER_DISABLE       0

#define TVP_OSD_RGB_CONV_MASK       0x3f00
#define TVP_OSD_RGB_CONV_HD_VID     0x0100
#define TVP_OSD_RGB_CONV_SD_VID     0x0500
#define TVP_OSD_RGB_CONV_HD_GRP     0x0a00
#define TVP_OSD_RGB_CONV_SD_GRP     0x0e00

#define TVP_OSD_BLEND_LEVEL_MASK    0xff

#define TVP_OSD_TRANS_LSB_MASK      0x06000000
#define TVP_OSD_TRANS_LSB_SHIFT     25
#define TVP_OSD_TRANS_ENABLE        0x01000000
#define TVP_OSD_TRANS_COLOR_MASK    0x00ffffff

// OSD_CFG register bits
#define TVP_FIELD_MODE_INTERLACED      0x1
#define TVP_FIELD_FLIP                 0x80
#define TVP_VIDEO_FIELD_FLIP           0x200
#define TVP_OSD_EN                     0x100
#define TVP_OSD_CFG_VBI_MASK           (0x7e | TVP_FIELD_FLIP | TVP_VIDEO_FIELD_FLIP)
#define TVP_OSD_CFG_VBI_SHIFT          1

#define TVP_OSD_CFG_VBI_480I_DEFAULT   ((16 << TVP_OSD_CFG_VBI_SHIFT) | TVP_FIELD_FLIP)
#define TVP_OSD_CFG_VBI_480P_DEFAULT   (38 << TVP_OSD_CFG_VBI_SHIFT)
#define TVP_OSD_CFG_VBI_720P_DEFAULT   ((26 << TVP_OSD_CFG_VBI_SHIFT) | TVP_VIDEO_FIELD_FLIP)
#define TVP_OSD_CFG_VBI_1080I_DEFAULT  ((18 << TVP_OSD_CFG_VBI_SHIFT) | TVP_VIDEO_FIELD_FLIP)
#define TVP_OSD_CFG_VBI_576_DEFAULT    ((16 << TVP_OSD_CFG_VBI_SHIFT) | TVP_FIELD_FLIP)
#define TVP_OSD_CFG_VBI_WVGA_DEFAULT   (33 << TVP_OSD_CFG_VBI_SHIFT)
#define TVP_OSD_CFG_VBI_WXGA_DEFAULT   (18 << TVP_OSD_CFG_VBI_SHIFT)

#define TVP_OSD_CFG_VBI_DEFAULT        (TVP_OSD_CFG_VBI_480I_DEFAULT)


// TVP_OSD_CFG_LOAD_EN register bit definitions
#define TVP_OSD_GPU0_LOAD_EN        0x1
#define TVP_OSD_GPU1_LOAD_EN        0x2
#define TVP_OSD_VID_LOAD_EN         0x4
#define TVP_OSD_STL_LOAD_EN         0x8
#define TVP_OSD_CUR_LOAD_EN         0x10
#define TVP_OSD_SWP_LOAD_EN         0x20



#define TVP_CUR_LD_ENABLE           1
#define TVP_CUR_BITMAP1             0
#define TVP_CUR_BITMAP2             2

#define TVP_CUR_MAX_SIZE            32


// TVP_OSD_VID_CFG register definitions
#define TVP_OSD_VID_RGB_CONV_DISABLE      0x2000
#define TVP_OSD_VID_AVG_FILTER_SELECT     0x1000
#define TVP_OSD_VID_RGB_CONV_SOURCE_CLIP  0x800
#define TVP_OSD_VID_RGB_CONV_601_SEL      0x400
#define TVP_OSD_VID_RGB_Y_ADJ_ENABLE      0x200
#define TVP_OSD_VID_RGB_VID_ENABLE        0x100
#define TVP_OSD_VID_CFG_DEFAULT           (TVP_OSD_BLEND_LEVEL_MASK         | \
                                           TVP_OSD_VID_AVG_FILTER_SELECT    | \
                                           TVP_OSD_VID_RGB_CONV_SOURCE_CLIP | \
                                           TVP_OSD_VID_RGB_CONV_601_SEL     | \
                                           TVP_OSD_VID_RGB_Y_ADJ_ENABLE)

// TVP_OSD_NTSC_OUT_CFG register definitions
#define TVP_OSD_NTSC_FIELD_FLIP           0x1000
#define TVP_OSD_NTSC_CAPTURE_START_MASK   0xff0
#define TVP_OSD_NTSC_CAPTURE_START_SHIFT  4
#define TVP_OSD_NTSC_YC_PIX               0x8
#define TVP_OSD_NTSC_WITH_OSD             0x4
#define TVP_OSD_NTSC_SQFILTER_EN          0x2
#define TVP_OSD_NTSC_OUT_EN               0x1
#endif