tvpsdram.h

ti的数字电视芯片 tvp9000的源码

#ifndef TVPSDRAM_P_DOT_H_IS_DEFINED
#define TVPSDRAM_P_DOT_H_IS_DEFINED
/***************************************************************************** 
*    Property of Texas Instruments Incorporated, Copyright 2004
*    All rights reserved
******************************************************************************/
/*********************************************************************
*
* Description:
*  TvpSdram.h contains all global defines for SDRAM.
*   
*   
**********************************************************************/
/*********************************************************************
*
* $Revision: $
*
* $History: TvpSdram.h $
* 
*********************************************************************/

// START_INIT Register bit definitions
#define TVP_SDRAM_START_INIT     0x1

// default configuration for MI_CR (Control Register)  Duplicate entries in TvpSdram.inc and .ins
#define TVP_SDRAM_RRD_DLY        0x00000001     // Delay between bank activations 0=2, 1=3

#define TVP_SDRAM_RAS_DLY_5      0x00000000     // Minimum delay of activation
#define TVP_SDRAM_RAS_DLY_6      0x00000002     //  to precharge a given bank
#define TVP_SDRAM_RAS_DLY_7      0x00000004     
#define TVP_SDRAM_RAS_DLY_MSK    0x00000006

#define TVP_SDRAM_RP_DLY         0x00000008     // Min delay of precharge activation 0=2, 1=3

#define TVP_SDRAM_RFC_DLY_8      0x00000000     // Min delay refresh to activate
#define TVP_SDRAM_RFC_DLY_9      0x00000010
#define TVP_SDRAM_RFC_DLY_10     0x00000020
#define TVP_SDRAM_RFC_DLY_MSK    0x00000030

#define TVP_SDRAM_R2W_DLY        0x00000040     // Read to Write Delay range 0=5, 1=6

#define TVP_SDRAM_W2R_DLY_2      0x00000000     // Write to Read Delay range
#define TVP_SDRAM_W2R_DLY_3      0x00000080
#define TVP_SDRAM_W2R_DLY_4      0x00000100
#define TVP_SDRAM_W2R_DLY_5      0x00000180
#define TVP_SDRAM_W2R_DLY_MSK    0x00000180

#define TVP_SDRAM_W2P_TIME_2     0x00000000     // Precharge time following write w/ auto close
#define TVP_SDRAM_W2P_TIME_3     0x00000200    
#define TVP_SDRAM_W2P_TIME_4     0x00000400    
#define TVP_SDRAM_W2P_TIME_5     0x00000600    
#define TVP_SDRAM_W2P_TIME_MSK   0x00000600

#define TVP_SDRAM_REFR_848       0x00000000     // Refresh period
#define TVP_SDRAM_REFR_1696      0x00000800 
#define TVP_SDRAM_REFR_1056      0x00001000 
#define TVP_SDRAM_REFR_2112      0x00001800 
#define TVP_SDRAM_REFR_MSK       0x00001800 
    
#define TVP_SDRAM_DISP_WID_640   0x00000000     // Display width in pixels
#define TVP_SDRAM_DISP_WID_720   0x00002000    
#define TVP_SDRAM_DISP_WID_1280  0x00004000    
#define TVP_SDRAM_DISP_WID_1920  0x00006000    
#define TVP_SDRAM_DISP_WID_MSK   0x00006000    

                                                // Memory type
#define TVP_SDRAM_MEM_TYP_8_512   0x00030000    // x8 DDR 512 half word pages
#define TVP_SDRAM_MEM_TYP_8_1024  0x00040000    // x8 DDR 1024 half word pages
#define TVP_SDRAM_MEM_TYP_16_512  0x00050000    // x16 DDR 512 half word pages
#define TVP_SDRAM_MEM_TYP_16_1024 0x00060000    // x16 DDR 1024 half word pages
#define TVP_SDRAM_MEM_TYP_MSK     0x00070000    // x16 DDR 512 half word pages

#define TVP_SDRAM_CAS_LAT_2      0x00000000     // CAS Latency in cycles
#define TVP_SDRAM_CAS_LAT_2_5    0x00080000
#define TVP_SDRAM_CAS_LAT_3      0x00100000
#define TVP_SDRAM_CAS_LAT_MSK    0x00180000

#define TVP_SDRAM_REDUCE_DRIVE   0x01000000     // Extended mode in EMR init

#define TVP_SDRAM_CKE_NOTLO      0x02000000     // Power saving mode not active
                                                //  Power Saving mode when bit=0
#define TVP_SDRAM_CKE_LO_INIT    0x04000000     // Init phase with CKE=0 in
                                                //  initialization for low power mode
#define TVP_SDRAM_DELAY_DQS_MSK  0x78000000   
#define TVP_SDRAM_DELAY_DQS(a)   (a<<27)   


// Client Values for use in Priority configuration
#define TVP_SDRAM_PRI_CLIENT_TX     17       // TX Demux
#define TVP_SDRAM_PRI_CLIENT_MK     16       // Microphone
#define TVP_SDRAM_PRI_CLIENT_SI     15       // Mpeg stills
#define TVP_SDRAM_PRI_CLIENT_BG     14       // Background
#define TVP_SDRAM_PRI_CLIENT_HI     13       // Host Interface
#define TVP_SDRAM_PRI_CLIENT_DM     12       // DMA
#define TVP_SDRAM_PRI_CLIENT_PS     11       // PES Parser
#define TVP_SDRAM_PRI_CLIENT_AD     10       // Audio Decoder
#define TVP_SDRAM_PRI_CLIENT_AO     9        // Audio Output Controller
#define TVP_SDRAM_PRI_CLIENT_VL     8        // VLD
#define TVP_SDRAM_PRI_CLIENT_FA     7        // Final Adder
#define TVP_SDRAM_PRI_CLIENT_MO     6        // Motion Compensation
#define TVP_SDRAM_PRI_CLIENT_DP     5        // Display Processor
#define TVP_SDRAM_PRI_CLIENT_NV     4        // NTSC Video
#define TVP_SDRAM_PRI_CLIENT_OS     3        // OSD
#define TVP_SDRAM_PRI_CLIENT_BB     2        // Bitblt
#define TVP_SDRAM_PRI_CLIENT_NONE   0        // Unused

#define TVP_SDRAM_PRI_CLIENT_DUMMY  18       // Identify an unused priority slot

#define TVP_SDRAM_PRI_CLIENT_MSK       31
#define TVP_SDRAM_MAX_CLIENTS          18
#define TVP_SDRAM_PRI_WORDS            4
#define TVP_SDRAM_CLIENTS_PER_PRI_WORD 6

// Sturctures
typedef unsigned long TvpSdramCfg;
typedef struct 
{
   unsigned char pri[19];     // 0 is SUPER priority client which may
                              //   interrupt all other clients 
                              // 1 is Highest
                              // 17 is lowest
} TvpSdramPri;


 // sdram prototypes
 
#ifdef __cplusplus
 extern "C" {
#endif
 
 void tvpSdramInit(TvpSdramCfg);          // setup the sdram configuration
 void tvpSdramPriRead(TvpSdramPri *);     // read sdram priorities
 void tvpSdramPriWrite(TvpSdramPri *);    // write sdram priorities
 
#ifdef __cplusplus
 };
#endif

#endif