tvpsdram.inc

ti的数字电视芯片 tvp9000的源码

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Copyright 2004 by Texas Instruments Incorporated. All rights reserved.
;; Property of Texas Instruments Incorporated. Restricted rights to use,
;; duplicate or disclose this code are granted through contract.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; $Revision: $
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; $Description: $
;;
;; Assembly include file for sdram
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                    
;; $History: TvpSdram.inc $
; 
;;      
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;; SDRAM Config Register same defs in sdram.h

TVP_SDRAM_RRD_DLY       .set  0x00000001    ; Delay between bank activations 0=2, 1=3

TVP_SDRAM_RAS_DLY_5     .set  0x00000000    ; Minimum delay of activation
TVP_SDRAM_RAS_DLY_6     .set  0x00000002    ;  to precharge a given bank
TVP_SDRAM_RAS_DLY_7     .set  0x00000004     
TVP_SDRAM_RAS_DLY_MSK   .set  0x00000006

TVP_SDRAM_RP_DLY        .set  0x00000008    ; Min delay of precharge activation 0=2, 1=3

TVP_SDRAM_RFC_DLY_8     .set  0x00000000    ; Min delay refresh to activate
TVP_SDRAM_RFC_DLY_9     .set  0x00000010
TVP_SDRAM_RFC_DLY_10    .set  0x00000020
TVP_SDRAM_RFC_DLY_MSK   .set  0x00000030

TVP_SDRAM_R2W_DLY       .set  0x00000040    ; Read to Write Delay range 0=5, 1=6

TVP_SDRAM_W2R_DLY_2     .set  0x00000000    ; Write to Read Delay range
TVP_SDRAM_W2R_DLY_3     .set  0x00000080
TVP_SDRAM_W2R_DLY_4     .set  0x00000100
TVP_SDRAM_W2R_DLY_5     .set  0x00000180
TVP_SDRAM_W2R_DLY_MSK   .set  0x00000180

TVP_SDRAM_W2P_TIME_2    .set  0x00000000    ; Precharge time following write w/ auto close
TVP_SDRAM_W2P_TIME_3    .set  0x00000200    
TVP_SDRAM_W2P_TIME_4    .set  0x00000400    
TVP_SDRAM_W2P_TIME_5    .set  0x00000600    
TVP_SDRAM_W2P_TIME_MSK  .set  0x00000600

TVP_SDRAM_REFR_848      .set  0x00000000    ; Refresh period
TVP_SDRAM_REFR_1696     .set  0x00000800 
TVP_SDRAM_REFR_1056     .set  0x00001000 
TVP_SDRAM_REFR_2112     .set  0x00001800 
TVP_SDRAM_REFR_MSK      .set  0x00001800 
    
TVP_SDRAM_DISP_WID_640  .set  0x00000000     ; Display width in pixels
TVP_SDRAM_DISP_WID_720  .set  0x00002000    
TVP_SDRAM_DISP_WID_1280 .set  0x00004000    
TVP_SDRAM_DISP_WID_1920 .set  0x00006000    
TVP_SDRAM_DISP_WID_MSK  .set  0x00006000    

                                             ; Memory type
TVP_SDRAM_MEM_TYP_8_512   .set  0x00030000   ; x8 DDR 512 half word pages
TVP_SDRAM_MEM_TYP_8_1024  .set  0x00040000   ; x8 DDR 1024 half word pages
TVP_SDRAM_MEM_TYP_16_512  .set  0x00050000   ; x16 DDR 512 half word pages
;TVP_SDRAM_MEM_TYP_16_1024 .set  0x00060000  ; x16 DDR 1024 half word pages
TVP_SDRAM_MEM_TYP_16_1024 .set  0x00070000   ; x16 DDR 1024 half word pages
TVP_SDRAM_MEM_TYP_MSK     .set  0x00070000   ; x16 DDR 512 half word pages

TVP_SDRAM_CAS_LAT_2       .set  0x00000000   ; CAS Latency in cycles
TVP_SDRAM_CAS_LAT_2_5     .set  0x00080000
TVP_SDRAM_CAS_LAT_3       .set  0x00100000
TVP_SDRAM_CAS_LAT_MSK     .set  0x00180000

TVP_SDRAM_REDUCE_DRIVE    .set  0x01000000   ; Extended mode in EMR init

TVP_SDRAM_CKE_NOTLO       .set  0x02000000   ; Power saving mode not active
                                             ;  Power Saving mode when bit=0
TVP_SDRAM_CKE_LO_INIT     .set  0x04000000   ; Init phase with CKE=0 in
                                             ;  initialization for low power mode
TVP_SDRAM_DELAY_DQS_MSK   .set  0x78000000   

; Note: We may place different build dependent values for default 
;  setups for QT, CVE, EVM

TVP_DDR_POWER               .set    (TVP_SDRAM_CKE_NOTLO | TVP_SDRAM_REDUCE_DRIVE)
TVP_RAS_CAS                 .set    (TVP_SDRAM_RFC_DLY_10 | TVP_SDRAM_RP_DLY    | TVP_SDRAM_RAS_DLY_6 | TVP_SDRAM_RRD_DLY)
TVP_DDR_DLY                 .set    (TVP_SDRAM_REFR_1696 | TVP_SDRAM_W2P_TIME_5 | TVP_SDRAM_W2R_DLY_4 | TVP_SDRAM_R2W_DLY)
TVP_SDRAMCFG_DAT            .set    (TVP_SDRAM_MEM_TYP_16_1024 | TVP_SDRAM_DISP_WID_720 | TVP_DDR_POWER | TVP_DDR_DLY | TVP_RAS_CAS)



TVP_HEADER_SDCF         .set    TVP_SDRAMCFG_DAT ; sdram config

TVP_HEADER_EBI00        .set    0x00000000      ; ebi CS0 config 0
TVP_HEADER_EBI01        .set    0x00000000      ; ebi CS0 config 1
TVP_HEADER_EBI02        .set    0x00000000      ; ebi CS0 config 2
TVP_HEADER_EBI03        .set    0x00000000      ; ebi CS0 config 3
TVP_HEADER_EBI04        .set    0x00000000      ; ebi CS0 config 4