tvpcp15.h

ti的数字电视芯片 tvp9000的源码

#ifndef TVPCP15_DOT_H_IS_DEFINED
#define TVPCP15_DOT_H_IS_DEFINED

/***************************************************************************** 
*    Property of Texas Instruments Incorporated, Copyright 2004
*    All rights reserved
******************************************************************************/
/*********************************************************************
*
* Description:
*  TvpCp15.h contains all global cp15 defines.
*   
*   
**********************************************************************/
/*********************************************************************
*
* $Revision: $
*
* $History: TvpCp15.h $
*  
*********************************************************************/

typedef unsigned long  TvpCp15Cmd;
typedef unsigned long  TvpCp15Data;


#define TVP_CP15_RD_ID       0      // CP15 R0.0 read id 
#define TVP_CP15_RD_CACHETYP 1      // CP15 R0.1 read cache type
#define TVP_CP15_RD_TCMSTAT  2      // CP15 R0.2 read TCM status
#define TVP_CP15_RD_CTRL     3      // CP15 R1.0 read control
#define TVP_CP15_RD_TTB      4      // CP15 R2.0 read ttb
#define TVP_CP15_RD_DOM      5      // CP15 R3.0 read domain
#define TVP_CP15_RD_DFS      6      // CP15 R5.0.0 read data fault status
#define TVP_CP15_RD_IFS      7      // CP15 R5.0.1 read instruction fault status
#define TVP_CP15_RD_FA       8      // CP15 R6.0 read fault address
#define TVP_CP15_RD_TLBLD    9      // CP15 R10.0 read tlb lock down
#define TVP_CP15_RD_FSCE     10     // CP15 R13.0.0 read fsce pid
#define TVP_CP15_RD_CTXID    11     // CP15 R13.0.1 read context id

#define TVP_CP15_WR_CTRL     0      // CP15 R1.0 write control
#define TVP_CP15_WR_TTB      1      // CP15 R2.0 write ttb
#define TVP_CP15_WR_DOM      2      // CP15 R3.0 write domain
#define TVP_CP15_WR_DFS      3      // CP15 R5.0.0 write data fault status
#define TVP_CP15_WR_IFS      4      // CP15 R5.0.1 write instruction fault status
#define TVP_CP15_WR_FA       5      // CP15 R6.0 write fault address
#define TVP_CP15_WR_FIDC     6      // CP15 R7.7.0 invalidate I&D cache
#define TVP_CP15_WR_FIC      7      // CP15 R7.5.0 invalidate I cache
#define TVP_CP15_WR_FICE     8      // CP15 R7.5.1 invalidate I cache entry
#define TVP_CP15_WR_FDC      9      // CP15 R7.6.0 invalidate D cache
#define TVP_CP15_WR_FDCE     10     // CP15 R7.6.1 invalidate D cache entry
#define TVP_CP15_WR_CDCE     11     // CP15 R7.10.1 clean D cache entry
#define TVP_CP15_WR_CFDCE    12     // CP15 R7.14.1 clean and invalidate D cache entry
#define TVP_CP15_WR_FDCEI    13     // CP15 R7.6.2 invalidate D cache entry index
#define TVP_CP15_WR_CDCEI    14     // CP15 R7.10.2 clean D cache entry index
#define TVP_CP15_WR_CFDCEI   15     // CP15 R7.14.2 clean and invalidate D cache entry index
#define TVP_CP15_WR_CDC      16     // CP15 R7.10.3 clean d cache
#define TVP_CP15_WR_PIL      17     // CP15 R7.13.1 prefetch I-line
#define TVP_CP15_WR_WFI      18     // CP15 R7.0.4 wait for interrupt
#define TVP_CP15_WR_DWB      19     // CP15 R7.10.4 drain write buffer
#define TVP_CP15_WR_FITLB    20     // CP15 R8.5.0 invalidate I TLB
#define TVP_CP15_WR_FITLBE   21     // CP15 R8.5.1 invalidate I TLB Entry
#define TVP_CP15_WR_FDTLB    22     // CP15 R8.6.0 invalidate D TLB
#define TVP_CP15_WR_FDTLBE   23     // CP15 R8.6.1 invalidate D TLB Entry
#define TVP_CP15_WR_FIDTLB   24     // CP15 R8.7.0 invalidate I&D TLB
#define TVP_CP15_WR_TLBLD    25     // CP15 R10.0.0 write tlb lock down
#define TVP_CP15_WR_FSCE     26     // CP15 R13.0.0 write fsce pid
#define TVP_CP15_WR_CTXID    27     // CP15 R13.0.1 write context id
#define TVP_CP15_WR_TSTCLND  28     // CP15 R7.10.3 test and clean D cache
#define TVP_CP15_WR_TSTCLNID 29     // CP15 R7.14.3 test, clean, invalidate D cache

#ifdef __cplusplus
extern "C" {
#endif

void tvpCp15RegWrite(TvpCp15Cmd, TvpCp15Data);          // cp 15 write command
unsigned long tvpCp15RegRead(TvpCp15Cmd, TvpCp15Data);  // cp 15 read command
#ifdef __cplusplus
};
#endif

#endif