tvpsdram.gin

ti的数字电视芯片 tvp9000的源码

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@;;
@;; Copyright 2004 by Texas Instruments Incorporated. All rights reserved.
@;; Property of Texas Instruments Incorporated. Restricted rights to use,
@;; duplicate or disclose this code are granted through contract.
@;;
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@;;
@;; $Revision: $
@;;
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@;;
@;; $Description: $
@;;
@;; Assembly include file for sdram
@;;
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@;;                    
@;; $History: TvpSdram.inc $
@; 
@;;      
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@;; SDRAM Config Register same defs in sdram.h

     .set   TVP_SDRAM_RRD_DLY       ,  0x00000001    @; Delay between bank activations 0=2, 1=3

     .set   TVP_SDRAM_RAS_DLY_5     ,  0x00000000    @; Minimum delay of activation
     .set   TVP_SDRAM_RAS_DLY_6     ,  0x00000002    @;  to precharge a given bank
     .set   TVP_SDRAM_RAS_DLY_7     ,  0x00000004     
     .set   TVP_SDRAM_RAS_DLY_MSK   ,  0x00000006

     .set   TVP_SDRAM_RP_DLY        ,  0x00000008    @; Min delay of precharge activation 0=2, 1=3

     .set   TVP_SDRAM_RFC_DLY_8     ,  0x00000000    @; Min delay refresh to activate
     .set   TVP_SDRAM_RFC_DLY_9     ,  0x00000010
     .set   TVP_SDRAM_RFC_DLY_10    ,  0x00000020
     .set   TVP_SDRAM_RFC_DLY_MSK   ,  0x00000030

     .set   TVP_SDRAM_R2W_DLY       ,  0x00000040    @; Read to Write Delay range 0=5, 1=6

     .set   TVP_SDRAM_W2R_DLY_2     ,  0x00000000    @; Write to Read Delay range
     .set   TVP_SDRAM_W2R_DLY_3     ,  0x00000080
     .set   TVP_SDRAM_W2R_DLY_4     ,  0x00000100
     .set   TVP_SDRAM_W2R_DLY_5     ,  0x00000180
     .set   TVP_SDRAM_W2R_DLY_MSK   ,  0x00000180

     .set   TVP_SDRAM_W2P_TIME_2    ,  0x00000000    @; Precharge time following write w/ auto close
     .set   TVP_SDRAM_W2P_TIME_3    ,  0x00000200    
     .set   TVP_SDRAM_W2P_TIME_4    ,  0x00000400    
     .set   TVP_SDRAM_W2P_TIME_5    ,  0x00000600    
     .set   TVP_SDRAM_W2P_TIME_MSK  ,  0x00000600

     .set   TVP_SDRAM_REFR_848      ,  0x00000000    @; Refresh period
     .set   TVP_SDRAM_REFR_1696     ,  0x00000800 
     .set   TVP_SDRAM_REFR_1056     ,  0x00001000 
     .set   TVP_SDRAM_REFR_2112     ,  0x00001800 
     .set   TVP_SDRAM_REFR_MSK      ,  0x00001800 
    
     .set   TVP_SDRAM_DISP_WID_640  ,  0x00000000     @; Display width in pixels
     .set   TVP_SDRAM_DISP_WID_720  ,  0x00002000    
     .set   TVP_SDRAM_DISP_WID_1280 ,  0x00004000    
     .set   TVP_SDRAM_DISP_WID_1920 ,  0x00006000    
     .set   TVP_SDRAM_DISP_WID_MSK  ,  0x00006000    

                                             @; Memory type
     .set   TVP_SDRAM_MEM_TYP_8_512   ,  0x00030000   @; x8 DDR 512 half word pages
     .set   TVP_SDRAM_MEM_TYP_8_1024  ,  0x00040000   @; x8 DDR 1024 half word pages
     .set   TVP_SDRAM_MEM_TYP_16_512  ,  0x00050000   @; x16 DDR 512 half word pages
@;TVP_SDRAM_MEM_TYP_16_1024 ,  0x00060000  @; x16 DDR 1024 half word pages
     .set   TVP_SDRAM_MEM_TYP_16_1024 ,  0x00070000   @; x16 DDR 1024 half word pages
     .set   TVP_SDRAM_MEM_TYP_MSK     ,  0x00070000   @; x16 DDR 512 half word pages

     .set   TVP_SDRAM_CAS_LAT_2       ,  0x00000000   @; CAS Latency in cycles
     .set   TVP_SDRAM_CAS_LAT_2_5     ,  0x00080000
     .set   TVP_SDRAM_CAS_LAT_3       ,  0x00100000
     .set   TVP_SDRAM_CAS_LAT_MSK     ,  0x00180000

     .set   TVP_SDRAM_REDUCE_DRIVE    ,  0x01000000   @; Extended mode in EMR init

     .set   TVP_SDRAM_CKE_NOTLO       ,  0x02000000   @; Power saving mode not active
                                             @;  Power Saving mode when bit=0
     .set   TVP_SDRAM_CKE_LO_INIT     ,  0x04000000   @; Init phase with CKE=0 in
                                             @;  initialization for low power mode
     .set   TVP_SDRAM_DELAY_DQS_MSK   ,  0x78000000   

@; Note: We may place different build dependent values for default 
@;  setups for QT, CVE, EVM

     .set   TVP_DDR_POWER               ,    (TVP_SDRAM_CKE_NOTLO | TVP_SDRAM_REDUCE_DRIVE)
     .set   TVP_RAS_CAS                 ,    (TVP_SDRAM_RFC_DLY_10 | TVP_SDRAM_RP_DLY    | TVP_SDRAM_RAS_DLY_6 | TVP_SDRAM_RRD_DLY)
     .set   TVP_DDR_DLY                 ,    (TVP_SDRAM_REFR_1696 | TVP_SDRAM_W2P_TIME_5 | TVP_SDRAM_W2R_DLY_4 | TVP_SDRAM_R2W_DLY)
     .set   TVP_SDRAMCFG_DAT            ,    (TVP_SDRAM_MEM_TYP_16_1024 | TVP_SDRAM_DISP_WID_720 | TVP_DDR_POWER | TVP_DDR_DLY | TVP_RAS_CAS)



     .set   TVP_HEADER_SDCF         ,    TVP_SDRAMCFG_DAT @; sdram config

     .set   TVP_HEADER_EBI00        ,    0x00000000      @; ebi CS0 config 0
     .set   TVP_HEADER_EBI01        ,    0x00000000      @; ebi CS0 config 1
     .set   TVP_HEADER_EBI02        ,    0x00000000      @; ebi CS0 config 2
     .set   TVP_HEADER_EBI03        ,    0x00000000      @; ebi CS0 config 3
     .set   TVP_HEADER_EBI04        ,    0x00000000      @; ebi CS0 config 4