📄 tvp9k_osd_def.h
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/*******************************************************************************
* @ModuleName :: TVP9K_OSD_Def.h
*
* @Copyright :: Copyright 2005- Texas Instruments, Inc.
*
* @Description :: Constants & Definitions for TVP9K OSD Module
*
* @History ::
*---------------------------------------
* 03-13-2005 W.Shi Created
*******************************************************************************/
#ifndef _TVP9K_OSD_DEF_H_
#define _TVP9K_OSD_DEF_H_
#define TVP9K_DDR_BASE_ADDR 0x10000000
#define TVP9K_OSD_REG_BASE_ADDR 0x00060000
//----------------------------------------------------------
#define TVP9K_OSD_SYS_CSR_BASE_ADDR (TVP9K_OSD_REG_BASE_ADDR + 0x0000)
typedef struct _TVP9K_OSD_SYS_CSR_ {
volatile UINT32 Config;
volatile UINT32 DispWidth;
volatile UINT32 DispHeight;
volatile UINT32 GpuRegionPrioSwitchEnable;
volatile UINT32 DispOutConfig;
volatile UINT32 NtscOutputConfig;
volatile UINT32 ConfigLoadEnable;
volatile UINT32 Reserved[16 - 7];
} TVP9K_OSD_SYS_CSR;
//----------------------------------------------------------
#define TVP9K_OSD_GPU_CONFIG_BASE_ADDR (TVP9K_OSD_REG_BASE_ADDR + 0x0040)
typedef struct _TVP9K_OSD_GPU_CSR_ {
volatile UINT32 Config;
volatile UINT32 MainAttrBaseAddr; // Quad-word address (unit = 16-byte)
volatile UINT32 AuxAttrBaseAddr; // Quad-word address (unit = 16-byte)
volatile UINT32 Reserved[16 - 3];
} TVP9K_OSD_GPU_CSR;
#define TVP9K_OSD_GPU_MAIN 0
#define TVP9K_OSD_GPU_AUX 1
enum _TI_DTV_OSD_REGION_enum_ {
TI_DTV_OSD_MAIN_REGION,
TI_DTV_OSD_AUX_REGION1,
TI_DTV_OSD_AUX_REGION2
};
typedef struct _TVP9K_OSD_REGION_CTRL_ {
UCHAR DisplayType; // bitmap only should be good enough
UCHAR *pRegionAttrBase; // Region Attribute table address
UCHAR *pBitmapBase; // Bitmap data address
UINT32 *pClutBase; // CLUT base address
short DispX, DispY; // Display position
short Width, Height; // Display size
short Stride; // number of bytes per scan line
} TVP9K_OSD_REGION_CTRL;
//----------------------------------------------------------
typedef struct _TVP9K_OSD_REGION_ATTR_ {
union {
UINT32 Data;
struct {
UINT32 DisplayPriority: 4;
UINT32 AntiFlickerOption: 1;
UINT32 AntiFlickerEnable: 1;
UINT32 ClutLoadEnable: 1;
UINT32 ClutSelDisable: 1;
UINT32 ClutOffset: 8;
UINT32 GlobalBlendingLevel: 8;
UINT32 BlendType: 2;
UINT32 BoxBlendEnable: 1;
UINT32 TransparencyEnable: 1;
UINT32 DisplayType: 4;
} Bits;
} Config;
UINT32 ImageBaseAddr; // Source image base address (bit-address)
UINT32 ImageWidth; // Source image Width in bits
UINT32 ClutBaseAddr; // Clut base address: Quad-word address (unit = 16-byte)
union {
UINT32 Data;
struct {
UINT32 :10;
UINT32 x: 11;
UINT32 y: 11;
} Bits;
} DispPosition;
union {
UINT32 Data;
struct {
UINT32 :10;
UINT32 w: 11;
UINT32 h: 11;
} Bits;
} DispSize;
union {
UINT32 Data;
struct {
UINT32 BoxBlendLevel: 8;
UINT32 RgbColor: 24;
} Bits;
} TransAttribute;
UINT32 NextRegionBaseAddr;
} TVP9K_OSD_REGION_ATTR;
#define TVP9K_OSD_GPU_BITMAP_1 0
#define TVP9K_OSD_GPU_BITMAP_2 1
#define TVP9K_OSD_GPU_BITMAP_4 2
#define TVP9K_OSD_GPU_BITMAP_8 3
#define TVP9K_OSD_GPU_RGB16_565 8 // RGB 16-bit Graphic Display
#define TVP9K_OSD_GPU_ARGB16_1555 10 // RGB 16-bit Graphic Display
#define TVP9K_OSD_GPU_ARGB16_4444 11 // RGB 16-bit Graphic Display with alpha blending factor
#define TVP9K_OSD_GPU_RGB24 12 // RGB 24-bit Graphic Display
#define TVP9K_OSD_GPU_ARGB24_6666 14 // RGB 24-bit Graphic Display with alpha blending factor
#define TVP9K_OSD_GPU_ARGB32 15 // RGB 32-bit Graphic Display with alpha blending factor
//----------------------------------------------------------
#define TVP9K_OSD_VIDEO_CSR_BASE_ADDR (TVP9K_OSD_REG_BASE_ADDR + 0x0080)
typedef struct _TVP9K_OSD_VIDEO_CSR_ {
volatile UINT32 VideoEnable; // 1 = Video Layer enable
volatile UINT32 Config;
volatile UINT32 DispPos;
volatile UINT32 DispSize;
volatile UINT32 TransConfig;
volatile UINT32 Reserved[16 - 5];
} TVP9K_OSD_VIDEO_CSR;
//----------------------------------------------------------
#define TVP9K_OSD_STILL_CSR_BASE_ADDR (TVP9K_OSD_REG_BASE_ADDR + 0x00C0)
typedef struct _TVP9K_OSD_STILL_CSR_ {
volatile UINT32 StillEnable; // 1 = Still Layer enable
volatile UINT32 Config;
volatile UINT32 DispPos;
volatile UINT32 DispSize;
volatile UINT32 ImgDataBaseAddr; // OSD Still source data base address (bit-address)
volatile UINT32 ImgDataStrideOffset; // Stride offset (Bit-size)
volatile UINT32 TransCtrl;
volatile UINT32 Reserved[16 - 7];
} TVP9K_OSD_STILL_CSR;
//----------------------------------------------------------
#define TVP9K_OSD_CURSOR_CSR_BASE_ADDR (TVP9K_OSD_REG_BASE_ADDR + 0x0100)
typedef struct _TVP9K_OSD_CURSOR_CSR_ {
volatile UINT32 CursorEnable; // 1 = Cursor Layer enable
volatile UINT32 Config;
volatile UINT32 DispPos;
volatile UINT32 DispSize;
volatile UINT32 ImgDataBaseAddr; // OSD Still source data base address (bit-address)
volatile UINT32 CursorPalette[4];
volatile UINT32 Reserved[16 - 9];
} TVP9K_OSD_CURSOR_CSR;
//----------------------------------------------------------
#define TVP9K_OSD_BACK_CSR_BASE_ADDR (TVP9K_OSD_REG_BASE_ADDR + 0x0140)
//
// RGB24 Color for OSD Background (R, G, B)
//
#define TVP9K_OSD_RGB_BLACK 0x000000
#define TVP9K_OSD_RGB_BLUE 0x0000FF
#define TVP9K_OSD_RGB_GREEN 0x00FF00
#define TVP9K_OSD_RGB_CYAN 0x00FFFF
#define TVP9K_OSD_RGB_RED 0xFF0000
#define TVP9K_OSD_RGB_MAGENTA 0xFF00FF
#define TVP9K_OSD_RGB_YELLOW 0xFFFF00
#define TVP9K_OSD_RGB_WHITE 0xFFFFFF
#define TVP9K_OSD_RGB_DARK_BLUE 0x000080
#define TVP9K_OSD_RGB_DARK_GREEN 0x008000
#define TVP9K_OSD_RGB_DARK_CYAN 0x008080
#define TVP9K_OSD_RGB_DARK_RED 0x800000
#define TVP9K_OSD_RGB_DARK_MAGENTA 0x800080
#define TVP9K_OSD_RGB_DARK_YELLOW 0x808000
#define TVP9K_OSD_RGB_DARK_GRAY 0x808080
#define TVP9K_OSD_RGB_LIGHT_GRAY 0x404040
#define TVP9K_OSD_RGB_MONEY_GREEN 0x004000
#define TVP9K_OSD_RGB_SKY_BLUE 0x000040
#define TVP9K_OSD_RGB_CREAM 0x400040
#define TVP9K_OSD_RGB_MEDIUM_GRAY 0x202020
//
// YCbCr Color for Sundial Background (Cb, Y, Cr)
//
#define TVP9K_OSD_YCBCR_BLACK 0x801080
#define TVP9K_OSD_YCBCR_RED 0x1d63ff
#define TVP9K_OSD_YCBCR_GREEN 0x960000
#define TVP9K_OSD_YCBCR_CYAN 0xb300cc
#define TVP9K_OSD_YCBCR_BLUE 0xF02870
#define TVP9K_OSD_YCBCR_MAGENTA 0x69ffff
#define TVP9K_OSD_YCBCR_YELLOW 0xe29d00
#define TVP9K_OSD_YCBCR_WHITE 0xff8080
#define TVP9K_OSD_YCBCR_DARK_BLUE 0x0f71f1
#define TVP9K_OSD_YCBCR_DARK_GREEN 0x4b3535
#define TVP9K_OSD_YCBCR_DARK_CYAN 0x5a26a6
#define TVP9K_OSD_YCBCR_DARK_RED 0x26da5a
#define TVP9K_OSD_YCBCR_DARK_MAGENTA 0x35cbcb
#define TVP9K_OSD_YCBCR_DARK_YELLOW 0x718f0f
#define TVP9K_OSD_YCBCR_DARK_GRAY 0x808080
#define TVP9K_OSD_YCBCR_LIGHT_GRAY 0xc08080
#define TVP9K_OSD_YCBCR_MONEY_GREEN 0xd07070
#define TVP9K_OSD_YCBCR_SKY_BLUE 0xc462ac
#define TVP9K_OSD_YCBCR_CREAM 0xfb8475
#define TVP9K_OSD_YCBCR_MEDIUM_GRAY 0xa08084
typedef struct _TVP9K_OSD_BACK_CSR_ {
volatile UINT32 BackColor;
volatile UINT32 Reserved[16 - 1];
} TVP9K_OSD_BACK_CSR;
//----------------------------------------------------------
#define TVP9K_OSD_SWITCH_CSR_BASE_ADDR (TVP9K_OSD_REG_BASE_ADDR + 0x0180)
typedef struct _TVP9K_OSD_SWITCH_CSR_ {
volatile UINT32 SwitchCtrlEnable; // 1 = Switch control Layer enable
volatile UINT32 Attribute;
} TVP9K_OSD_SWITCH_CSR;
typedef struct _TVP9K_OSD_REG_ {
volatile TVP9K_OSD_SYS_CSR SysCsr; // OSD Sys Config/Status Registers (OSD_BASE + 0x0000)
volatile TVP9K_OSD_GPU_CSR GpuCsr; // OSD Graphics Layer Config/Status Registers (OSD_BASE + 0x0040)
volatile TVP9K_OSD_VIDEO_CSR VideoCsr; // OSD Video Layer Config/Status Registers (OSD_BASE + 0x0080)
volatile TVP9K_OSD_STILL_CSR StillCsr; // OSD Still Layer Config/Status Registers (OSD_BASE + 0x00C0)
volatile TVP9K_OSD_CURSOR_CSR CursorCsr; // OSD Cursor Layer Config/Status Registers (OSD_BASE + 0x0100)
volatile TVP9K_OSD_BACK_CSR BackCsr; // OSD Background Layer Config/Status Registers (OSD_BASE + 0x0140)
volatile TVP9K_OSD_SWITCH_CSR SwitchCsr; // OSD Switch Plane Layer Config/Status Registers (OSD_BASE + 0x0180)
} TVP9K_OSD_REG;
//------------------------------------------------------------
// Defined in "TiDTV_OSD.c"
//
void TiDTV_InitOSD(void);
void TiDTV_OsdSysConfig(UINT32 SysConfig, UINT32 DispWidth, UINT32 DispHeight,
UINT32 DispOutConfig, UINT32 NtscConfig);
void TiDTV_OsdSysCtrl(int EnableFlag);
void TiDTV_OsdCreateRegionAttr(TVP9K_OSD_REGION_CTRL *pRegionCtrl);
void TiDTV_OsdLinkRegionAttr(TVP9K_OSD_REGION_CTRL *pRegionCtrl1, TVP9K_OSD_REGION_CTRL *pRegionCtrl2);
void TiDTV_OsdGpuCtrl(int GpuID, int EnableFlag);
void TiDTV_OsdSetRegionAttr(int GpuID, TVP9K_OSD_REGION_CTRL *pRegionCtrl);
void TiDTV_OsdSetRegionBitmap(int RegionID, UCHAR *pBitmapBase);
void TiDTV_OsdSetRegionDispPos(int RegionID, short DispX, short DispY);
void TiDTV_OsdVideoConfig(UINT32 VideoConfig, UINT32 DispX, UINT32 DispY,
UINT32 DispWidth, UINT32 DispHeight, UINT32 TransConfig);
void TiDTV_OsdVideoCtrl(int EnableFlag);
void TiDTV_OsdVideoChgDispPos(UINT32 DispX, UINT32 DispY);
void TiDTV_OsdVideoChgDispSize(UINT32 DispWidth, UINT32 DispHeight);
void TiDTV_OsdSetBackgroundColor(UINT32 RgbColor, UINT32 YCbCrColor);
void TiDTV_VideoBackColorCtrl(int ForceBackColor);
#endif /* _TVP9K_OSD_DEF_H_ */
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