9315addr.h

ads1.2 下的EP9315的源代码(UART)

//=============================================================================
// File Name : 2410addr.h
// Function  : S3C2410 Define Address Register
// Program   : Shin, On Pil (SOP)
// Date      : May 06, 2002
// Version   : 0.0
// History
//   0.0 : Programming start (February 15,2002) -> SOP
//         INTERRUPT rPRIORITY 0x4a00000a -> 0x4a00000c       (May 02, 2002 SOP)
//         RTC BCD DAY and DATE Register Name Correction      (May 06, 2002 SOP) 
//=============================================================================

//#ifndef __2410ADDR_H__
//#define __2410ADDR_H__

/*#ifdef __cplusplus*/
//extern "C" {
//*/#endif*/

//#include "option.h"(*(volatile unsigned *)0x48000000)
//System Controller
#define  sys_controller 0x80930000
#define  PwrSts       (*(volatile unsigned int *)sys_controller)
#define  PwrCnt       (*(volatile unsigned int *)0x80930004) 
#define  Halt         (*(volatile unsigned int *)0x80930008) 
#define  Standby      (*(volatile unsigned int *)sys_controller + 0xc) 
#define  TEOI         (*(volatile unsigned int *)sys_controller + 0x18) 
#define  STFClr       (*(volatile unsigned int *)sys_controller + 0x1c) 
#define  ClkSet1      (*(volatile unsigned int *)sys_controller + 0x20) 
#define  ClkSet2      (*(volatile unsigned int *)sys_controller + 0x24) 
#define  ScratchReg0  (*(volatile unsigned int *)sys_controller + 0x40) 
#define  ScratchReg1  (*(volatile unsigned int *)sys_controller + 0x44) 
#define  APBWait      (*(volatile unsigned int *)sys_controller + 0x50) 
#define  BusMstrArb   (*(volatile unsigned int *)sys_controller + 0x54) 
#define  BootModeClr  (*(volatile unsigned int *)sys_controller + 0x58) 
#define  DeviceCfg    (*(volatile unsigned long *)0x80930080) 
#define VidClkDiv     (*(volatile unsigned int *)sys_controller + 0x84) 
#define MIRClkDiv     (*(volatile unsigned int *)sys_controller + 0x88) 
#define I2SClkDiv     (*(volatile unsigned int *)sys_controller + 0x8c) 
#define KeyTchClkDiv  (*(volatile unsigned int *)sys_controller + 0x90) 
#define ChipID        (*(volatile unsigned int *)sys_controller + 0x94) 
#define SysCfg        (*(volatile unsigned int *)sys_controller + 0x9c) 
#define SysSWLock     (*(volatile unsigned int *)sys_controller + 0xc0) 

//INTERRUPT
#define VICbase  0x800b0000 //0x800c0000
#define VICxIRQStatus    (*(volatile unsigned int *)VICbase + 0x0000) //Bus width & wait status
#define VICxFIQStatus    (*(volatile unsigned int *)VICbase + 0x0004) //Boot ROM control
#define VICxRawIntr      (*(volatile unsigned int *)VICbase + 0x0008) //BANK1 control
#define VIC1IntSelect    (*(volatile unsigned int *)0x800b000C) //BANK2 cControl
#define VIC1IntEnable    (*(volatile unsigned int *)0x800b0010) //BANK3 control
#define VICxIntEnClear   (*(volatile unsigned int *)VICbase + 0x0014) //BANK4 control
#define VIC1SoftInt      (*(volatile unsigned int *)0x800b0018) //BANK5 control
#define VICxSoftIntClear (*(volatile unsigned int *)VICbase + 0x001C) //BANK6 control
#define VICxProtection   (*(volatile unsigned int *)VICbase + 0x0020) //BANK7 control
#define VIC1VectAddr     (*(volatile unsigned int *)0x800b0030) //DRAM/SDRAM refresh
#define VICxDefVectAddr  (*(volatile unsigned int *)VICbase + 0x0034) //Flexible Bank Size
#define VICxVectAddr0    (*(volatile unsigned int *)VICbase + 0x0100) //Mode register set for SDRAM
#define VICxVectAddr1    (*(volatile unsigned int *)VICbase + 0x0104) //Mode register set for SDRAM
#define VIC1VectAddr2    (*(volatile unsigned int *)0x800b0108) //Bus width & wait status
#define VICxVectAddr3    (*(volatile unsigned int *)VICbase + 0x010C) //Boot ROM control
#define VICxVectAddr4    (*(volatile unsigned int *)VICbase + 0x0110) //BANK1 control
#define VICxVectAddr5    (*(volatile unsigned int *)VICbase + 0x0114) //BANK2 cControl
#define VICxVectAddr6    (*(volatile unsigned int *)VICbase + 0x0118) //BANK3 control
#define VICxVectAddr7    (*(volatile unsigned int *)VICbase + 0x011C) //BANK4 control
#define VICxVectAddr8    (*(volatile unsigned int *)VICbase + 0x0120) //BANK5 control
#define VICxVectAddr9    (*(volatile unsigned int *)VICbase + 0x0124) //BANK6 control
#define VICxVectAddr10   (*(volatile unsigned int *)VICbase + 0x0128) //BANK7 control
#define VICxVectAddr11   (*(volatile unsigned int *)VICbase + 0x012C) //DRAM/SDRAM refresh
#define VICxVectAddr12   (*(volatile unsigned int *)VICbase + 0x0130) //Flexible Bank Size
#define VICxVectAddr13   (*(volatile unsigned int *)VICbase + 0x0134) //Mode register set for SDRAM
#define VICxVectAddr14   (*(volatile unsigned int *)VICbase + 0x0138) //Mode register set for SDRAM
#define VICxVectAddr15   (*(volatile unsigned int *)VICbase + 0x013C) //Bus width & wait status
#define VICxVectCntl0    (*(volatile unsigned int *)VICbase + 0x0200) //Boot ROM control
#define VICxVectCntl1    (*(volatile unsigned int *)VICbase + 0x0204) //BANK1 control
#define VIC1VectCntl2    (*(volatile unsigned int *)0x800b0208) //BANK2 cControl
#define VICxVectCntl3    (*(volatile unsigned int *)VICbase + 0x020C) //BANK3 control
#define VICxVectCntl4    (*(volatile unsigned int *)VICbase + 0x0210) //BANK4 control
#define VICxVectCntl5    (*(volatile unsigned int *)VICbase + 0x0214)
#define VICxVectCntl6    (*(volatile unsigned int *)VICbase + 0x0218) //BANK5 control
#define VICxVectCntl7    (*(volatile unsigned int *)VICbase + 0x021c) //BANK6 control
#define VICxVectCntl8    (*(volatile unsigned int *)VICbase + 0x0220) //BANK7 control
#define VICxVectCntl9    (*(volatile unsigned int *)VICbase + 0x0224) //DRAM/SDRAM refresh
#define VICxVectCntl10   (*(volatile unsigned int *)VICbase + 0x0228) //Flexible Bank Size
#define VICxVectCntl11   (*(volatile unsigned int *)VICbase + 0x022C) //Mode register set for SDRAM
#define VICxVectCntl12   (*(volatile unsigned int *)VICbase + 0x0230) //Mode register set for SDRAM
#define VICxVectCntl13   (*(volatile unsigned int *)VICbase + 0x0234) //Bus width & wait status
#define VICxVectCntl14   (*(volatile unsigned int *)VICbase + 0x0238) //Boot ROM control
#define VICxVectCntl15   (*(volatile unsigned int *)VICbase + 0x023C) //BANK1 control
#define VICxPeriphID0    (*(volatile unsigned int *)VICbase + 0x0FE0) //BANK2 cControl
#define VICxPeriphID1    (*(volatile unsigned int *)VICbase + 0x0FE4) //BANK3 control
#define VICxPeriphID2    (*(volatile unsigned int *)VICbase + 0x0FE8) //BANK4 control
#define VICxPeriphID3    (*(volatile unsigned int *)VICbase + 0x0FEC) //BANK5 control

//lcd

//Graphics Accelerator

//Ethernet LAN Controller

//DMA

//usb host

//PCMCIA

//ram rom flash
#define flash_controller_baseaddr 0x80060000
#define GlConfig      (*(volatile unsigned int *)flash_controller_baseaddr + 0x4) 
#define RefrshTimr    (*(volatile unsigned int *)flash_controller_baseaddr + 0x8) 
#define BootSts       (*(volatile unsigned int *)flash_controller_baseaddr + 0xc) 
#define SDRAMDevCfg0  (*(volatile unsigned int *)flash_controller_baseaddr + 0x10) 
#define SDRAMDevCfg1  (*(volatile unsigned int *)flash_controller_baseaddr + 0x14) 
#define SDRAMDevCfg2  (*(volatile unsigned int *)flash_controller_baseaddr + 0x18) 
#define SDRAMDevCfg3  (*(volatile unsigned int *)flash_controller_baseaddr + 0x1c) 

//uart1
#define uart_controller_baseaddr 0x808c0000
#define UART1Data              (*(volatile unsigned char *)uart_controller_baseaddr) 
#define UART1RXSts             (*(volatile unsigned int *)uart_controller_baseaddr + 0x4) 
#define UART1LinCtrlHigh       (*(volatile unsigned int *)0x808c0008) 
#define UART1LinCtrlMid  (*(volatile unsigned int *)0x808c000c) 
#define UART1LinCtrlLow  (*(volatile unsigned int *)0x808c0010) 
#define UART1Ctrl  (*(volatile unsigned int *)0x808c0014) 
#define UART1Flag  (*(volatile unsigned int *)0x808c0018) 
#define UART1IntIDIntClr      (*(volatile unsigned int *)0x808c001c) 
#define UART1DMACtrl    (*(volatile unsigned int *)flash_controller_baseaddr + 0x28) 
#define UART1ModemCtrl      (*(volatile unsigned int *)flash_controller_baseaddr + 0x100) 
#define UART1ModemSts  (*(volatile unsigned int *)flash_controller_baseaddr + 0x104) 
#define UART1HDLCCtrl  (*(volatile unsigned int *)flash_controller_baseaddr + 0x20c) 
#define UART1HDLCAddMtchVal  (*(volatile unsigned int *)flash_controller_baseaddr + 0x210) 
#define UART1HDLCAddMask  (*(volatile unsigned int *)flash_controller_baseaddr + 0x214) 
#define UART1HDLCRXInfoBuf      (*(volatile unsigned int *)flash_controller_baseaddr +0x218) 
#define UART1HDLCSts    (*(volatile unsigned int *)flash_controller_baseaddr + 0x21c) 

//uart2

//uart3

//irDA

//timers

//Watchdog Timer
#define Watchdog  (*(volatile unsigned int *)0x80940000) 
#define WDStatus  (*(volatile unsigned int *)0x80940004) 

//RTC

//I2S

//AC97

//ssp

//pwm

//Touch Screen

//Keypad

//IDE

//GPIO
#define gpio_con_baseaddr + 0x  0x80840000
#define PADR           (*(volatile unsigned int *)gpio_con_baseaddr) //BANK2 cControl
#define PBDR           (*(volatile unsigned int *)gpio_con_baseaddr + 0x4) //BANK3 control
#define PCDR           (*(volatile unsigned int *)gpio_con_baseaddr + 0x8) //BANK4 control
#define PDDR           (*(volatile unsigned int *)gpio_con_baseaddr + 0xc) //BANK5 control
#define PADDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x10) //BANK6 control
#define PBDDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x14) //BANK7 control
#define PCDDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x18) //DRAM/SDRAM refresh
#define PDDDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x1c) //Flexible Bank Size
#define PEDR           (*(volatile unsigned int *)gpio_con_baseaddr + 0x20) //Mode register set for SDRAM
#define PEDDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x24) //Mode register set for SDRAM
#define PFDR           (*(volatile unsigned int *)gpio_con_baseaddr + 0x30) //BANK2 cControl
#define PFDDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x34) //BANK3 control
#define PGDR           (*(volatile unsigned int *)gpio_con_baseaddr + 0x38) //BANK4 control
#define PGDDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x3c) //BANK5 control
#define PHDR           (*(volatile unsigned int *)gpio_con_baseaddr + 0x40) //BANK6 control
#define PHDDR          (*(volatile unsigned int *)gpio_con_baseaddr + 0x44) //BANK7 control
#define GPIOFIntType1  (*(volatile unsigned int *)gpio_con_baseaddr + 0x4c) //DRAM/SDRAM refresh
#define GPIOFIntType2  (*(volatile unsigned int *)gpio_con_baseaddr + 0x50) //Flexible Bank Size
#define GPIOFEOI       (*(volatile unsigned int *)gpio_con_baseaddr + 0x54) //Mode register set for SDRAM
#define GPIOFIntEn     (*(volatile unsigned int *)gpio_con_baseaddr + 0x58) //Mode register set for SDRAM
#define IntStsF        (*(volatile unsigned int *)gpio_con_baseaddr + 0x5c) //Bus width & wait status
#define RawIntStsF     (*(volatile unsigned int *)gpio_con_baseaddr + 0x60) //Boot ROM control
#define GPIOFDB        (*(volatile unsigned int *)gpio_con_baseaddr + 0x64) //BANK1 control
#define GPIOAIntType1  (*(volatile unsigned int *)gpio_con_baseaddr + 0x90) //BANK2 cControl
#define GPIOAIntType2  (*(volatile unsigned int *)gpio_con_baseaddr + 0x94) //BANK3 control
#define GPIOAEOI       (*(volatile unsigned int *)gpio_con_baseaddr + 0x98) //BANK4 control
#define GPIOAIntEn     (*(volatile unsigned int *)gpio_con_baseaddr + 0x9c) //BANK5 control
#define IntStsA        (*(volatile unsigned int *)gpio_con_baseaddr + 0xa0) //BANK6 control
#define RawIntStsA     (*(volatile unsigned int *)gpio_con_baseaddr + 0xa4) //BANK7 control
#define GPIOADB        (*(volatile unsigned int *)gpio_con_baseaddr + 0xa8) //DRAM/SDRAM refresh
#define GPIOBIntType1  (*(volatile unsigned int *)gpio_con_baseaddr + 0xac) //Flexible Bank Size
#define GPIOBIntType2  (*(volatile unsigned int *)gpio_con_baseaddr + 0xb0) //Mode register set for SDRAM
#define GPIOBEOI       (*(volatile unsigned int *)gpio_con_baseaddr + 0xb4) //Mode register set for SDRAM
#define GPIOBIntEn     (*(volatile unsigned int *)gpio_con_baseaddr + 0xb8) //Bus width & wait status
#define IntStsB        (*(volatile unsigned int *)gpio_con_baseaddr + 0xbc) //Boot ROM control
#define RawIntStsB     (*(volatile unsigned int *)gpio_con_baseaddr + 0xc0) //BANK1 control
#define GPIOBDB        (*(volatile unsigned int *)gpio_con_baseaddr + 0xc4) //BANK2 cControl
#define EEDrive        (*(volatile unsigned int *)gpio_con_baseaddr + 0xc8) //BANK3 control

#define COMMRX 2
#define COMMTX 3
#define TC1OI  4
#define TC2OI  5
#define AACINTR 6
#define DMAM2P0 7
#define DMAM2P1 8
#define DMAM2P2 9
#define DMAM2P3 10
#define DMAM2P4 11
#define DMAM2P5 12
#define DMAM2P6 13
#define DMAM2P7 14
#define DMAM2P8 15
#define DMAM2P9 16
#define DMAM2M0 17
#define DMAM2M1 18
#define GPIO0INTR 19
#define GPIO1INTR 20
#define GPIO2INTR 21
#define GPIO3INTR 22
#define UART1RXINTR1 1<<23
#define UART1TXINTR1 24
#define UART2RXINTR2 25
#define UART2TXINTR2 26
#define UART3RXINTR3 27
#define UART3TXINTR3 28
#define INT_KEY 29
#define INT_TOUCH 30

#define INT_EXT0 32
#define NT_EXT1  33
#define INT_EXT2 34
#define TINTR 35
#define WEINT 36
#define INT_RTC  37

#define INT_IrDA 38
#define INT_MAC 39
#define INT_EXT3 40
#define INT_PROG 41
#define CLK1HZ 42
#define V_SYNC 43
#define INT_VIDEO_FIFO 44
#define INT_SSP1RX 45
#define INT_SSP1TX 46
#define GPIO4INTR 47
#define GPIO5INTR 48
#define GPIO6INTR 49
#define GPIO7INTR 50
#define TC3OI     51
#define INT_UART1 52
#define SSPINTR   53
#define INT_UART2 54
#define INT_UART3 55
#define USHINTR   56
#define INT_PME 57
#define INT_DSP 58
#define GPIOINTR 59
#define SAIINTR 60