ep9315.s

ads1.2 下的EP9315的源代码(UART)

 ;IMPORT  ||Image$$ZI$$Limit||
  ;IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
	;IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise
	;;IMPORT  |Image$$ZI$$Limit|  ; to zero initialise
;Pre-defined constants
USERMODE    EQU 	0x10
FIQMODE     EQU 	0x11
IRQMODE     EQU 	0x12
SVCMODE     EQU 	0x13
ABORTMODE   EQU 	0x17
UNDEFMODE   EQU 	0x1b
MODEMASK    EQU 	0x1f
NOINT       EQU 	0xc0
_STACK_BASEADDRESS EQU 0x010ff000
;The location of stacks
UserStack	EQU	(_STACK_BASEADDRESS-0x3800)	;0x33ff4800 ~ 
SVCStack          EQU	(_STACK_BASEADDRESS-0x2800) 	;0x33ff5800 ~
UndefStack	EQU	(_STACK_BASEADDRESS-0x2400) 	;0x33ff5c00 ~
AbortStack	EQU	(_STACK_BASEADDRESS-0x2000) 	;0x33ff6000 ~
IRQStack          EQU	(_STACK_BASEADDRESS-0x1000)	;0x33ff7000 ~
FIQStack	EQU	(_STACK_BASEADDRESS-0x0)	;0x33ff8000 ~ 
R1_M               EQU      1
R1_I    EQU        (1<<12)
R1_C    EQU        (1<<2) 
;system clock
clock_com EQU 0x0099b8e7
  IMPORT  main    ; The main entry of mon program 
 ; IMPORT  SdramCfg
  EXPORT Reset
  AREA   Init ,CODE,READONLY
  ENTRY
Reset 
       ldr    pc,resrtaddr
	   ldr    pc,undefinedaddr
	   ldr    pc,swi_addr
	   ldr    pc,prefetchaddr
	   ldr    pc,dataabortaddr
	   ldr    pc,_not_used
	   ldr    pc,=0x808b0030
	   ldr    pc,_fig
resrtaddr       dcd   ResetHandler
undefinedaddr   dcd   HandlerUndef
swi_addr        dcd   HandlerSWI
prefetchaddr    dcd   HandlerPabort
dataabortaddr   dcd   HandlerDabort
_not_used       dcd   0
_irg            dcd   HandlerIRQ
_fig            dcd   HandlerFIQ
ResetHandler
    mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr cpsr_cxsf,r0
	ldr r0,=0x80940000 ;
	ldr r1,=0xaa55
	str r1,[r0]
	bl cpu_init_crit
	ldr r0,=0x800b0010
	ldr r1,=0x0
	str r1,[r0]
	ldr r0,=0x800c0010
	ldr r1,=0x0
	str r1,[r0]
	ldr r0,=0x80930020
	ldr r1,=clock_com
	str r1,[r0]
    bl     InitStacks
    bl      SdramCfg
    ldr     r0, =0x107c
    mcr     p15, 0, r0, c1, c0, 0
    b       main
cpu_init_crit
    mrc  p15,0,r0,c1,c0,0      ; disable ICache
    bic  r0,r0,#0x0
    mcr  p15,0,r0,c1,c0,0
    
    mrc  p15,0,r0,c1,c0,0      ; disable DCache
    bic  r0,r0,#0x0
    mcr  p15,0,r0,c1,c0,0
	
	mrc  p15,0,r0,c1,c0,0      ; disable MMU 
    bic  r0,r0,#0x0
    mcr  p15,0,r0,c1,c0,0
    mov pc,lr
InitStacks
	;Don't use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE|NOINT
	msr	cpsr_cxsf,r1		;UndefMode
	ldr	sp,=UndefStack
	
	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1		;AbortMode
	ldr	sp,=AbortStack

	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		;IRQMode
	ldr	sp,=IRQStack
    
	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1		;FIQMode
	ldr	sp,=FIQStack

	bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		;SVCMode
	ldr	sp,=SVCStack
	
	;USER mode has not be initialized.
	
	mov	pc,lr 
	;The LR register won't be valid if the current mode is not SVC mode.
SdramCfg
    ldr r0,=0x80060004
	ldr r1,=0x80000001
	str r1,[r0]
	ldr r0,=0x80060010
	ldr r1,=0x2A0028
	str r1,[r0]
	ldr r0,=0x80060014
	ldr r1,=0x01240008
	str r1,[r0]
	ldr r0,=0x80060018
	ldr r1,=0x01240008
	str r1,[r0]
	ldr r0,=0x8006001C
	ldr r1,=0x220028
	str r1,[r0]
	ldr r0,=0x80060008
	ldr r1,=0x204
	str r1,[r0]
	 ldr r0,=0x80060004
	ldr r1,=0x80000000
	str r1,[r0]
    mov	pc,lr
HandlerUndef
     bl    HandlerUndef
HandlerSWI
     bl  HandlerSWI
HandlerPabort
     bl   HandlerPabort     
HandlerDabort
     bl   HandlerDabort 
HandlerIRQ 
     bl   HandlerIRQ
HandlerFIQ
    bl    HandlerFIQ 
	end