_primary.vhd

来自「利用verilog实现单片机的反向设计。编程环境为modelsim6.0」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity \all\ is
    port(
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        rom_addr        : out    vl_logic_vector(15 downto 0);
        int             : in     vl_logic;
        int_v           : in     vl_logic_vector(7 downto 0);
        reti            : out    vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0);
        data_out        : out    vl_logic_vector(7 downto 0);
        ext_addr        : out    vl_logic_vector(15 downto 0);
        write           : out    vl_logic;
        p0_in           : in     vl_logic_vector(7 downto 0);
        p1_in           : in     vl_logic_vector(7 downto 0);
        p2_in           : in     vl_logic_vector(7 downto 0);
        p3_in           : in     vl_logic_vector(7 downto 0);
        p0_out          : out    vl_logic_vector(7 downto 0);
        p1_out          : out    vl_logic_vector(7 downto 0);
        p2_out          : out    vl_logic_vector(7 downto 0);
        p3_out          : out    vl_logic_vector(7 downto 0)
    );
end \all\;