_primary.vhd

来自「利用verilog实现单片机的反向设计。编程环境为modelsim6.0」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity IndiAddr is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        addr            : in     vl_logic_vector(7 downto 0);
        data_in         : in     vl_logic_vector(7 downto 0);
        wr              : in     vl_logic;
        wr_bit          : in     vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0);
        sel             : in     vl_logic;
        bank            : in     vl_logic_vector(1 downto 0)
    );
end IndiAddr;