_primary.vhd

来自「利用verilog实现单片机的反向设计。编程环境为modelsim6.0」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity reg8r is
    port(
        clk             : in     vl_logic;
        \in\            : in     vl_logic_vector(7 downto 0);
        \out\           : out    vl_logic_vector(7 downto 0);
        rd              : in     vl_logic
    );
end reg8r;