_primary.vhd

来自「利用verilog实现单片机的反向设计。编程环境为modelsim6.0」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity ext_addr_sel is
    port(
        clk             : in     vl_logic;
        \select\        : in     vl_logic;
        write           : in     vl_logic;
        dptr_hi         : in     vl_logic_vector(7 downto 0);
        dptr_lo         : in     vl_logic_vector(7 downto 0);
        ri              : in     vl_logic_vector(7 downto 0);
        addr_out        : out    vl_logic_vector(15 downto 0)
    );
end ext_addr_sel;