📄 debug.lst
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putchar( mspParam.DataByte_Low );
putchar( mspParam.DataByte_High );
putstr("\r\nMSP Read");
break;
} // End of switch(dev_cmd)
break;
}
#endif
744 3
745 3 #if TV_ENABLE
746 3 case DEV_PHLIPS_TUNER:
747 3 {
748 4 switch(UART_EXT_CMD)
749 4 {
750 5 case URCMD_PHLIPS_TUNER_SET_FREQ: // Write and get status
751 5 {
752 6 XDATA TunerProgramType tunerParam;
753 6 putstr("\r\nTuner write");
754 6 tunerParam.ProgDivide = ((WORD)UART_EXT_CMD_MS_DAT2 <<8) + UART_EXT_CMD_MS_DAT1; /
-/ Program divider 2 byte (n14-n0)
755 6 tunerParam.ControlInfo1 = UART_EXT_CMD_MS_DAT3; // Control information byte 1
756 6 tunerParam.ControlInfo2 = UART_EXT_CMD_MS_DAT4; // Control information byte 1(P7-P
-0)
757 6 #if 0//( TUNER_IS_PHILIPS )
tunerParam.AuxilliaryByte = UART_EXT_CMD_MS_DAT5; // Auxilliary byte
#endif
760 6
761 6 i2c_AccessStart(TN_PROG_I2C_ADDR, I2C_WRITE);
762 6 i2c_SendByte(tunerParam.ProgDivide>>8);
763 6 Delay1ms(1);
764 6 i2c_SendByte(tunerParam.ProgDivide&0xff);
765 6 Delay1ms(1);
766 6 i2c_SendByte(tunerParam.ControlInfo1);
767 6 Delay1ms(1);
768 6 i2c_SendByte(g_bTunerParm.ControlInfo2);
769 6 Delay1ms(1);
770 6 i2c_Stop();
771 6
772 6 UART_CMD_MS_DAT = 0;//devTunerWrite(&tunerParam);
773 6 putchar(0xF2);
774 6 putchar( UART_CMD_MS_DAT );
775 6 }
776 5 break;
777 5 case URCMD_PHLIPS_TUNER_GET_STATUS:
778 5 putstr("\r\nTuner Read");
779 5 UART_CMD_MS_DAT = devTunerGetStatus(20);
780 5 putchar(0xF2);
781 5 putchar( UART_CMD_MS_DAT );
782 5 break;
783 5 } // End of switch(dev_cmd)
784 4 break;
785 4 }
786 3 // other device ...
787 3 #endif
788 3
789 3 // I2C Debug ...
790 3 case 0xf0: // I2C Write Bytes(Has sub address)
791 3 i2cBurstWriteBytes( g_UartCommand.Buffer[_UART_CMD_INDEX3_],
C51 COMPILER V8.01 DEBUG 11/28/2006 08:08:03 PAGE 14
792 3 g_UartCommand.Buffer[_UART_CMD_INDEX4_],
793 3 &(g_UartCommand.Buffer[_UART_CMD_INDEX5_]),
794 3 UART_CMD_EXT_LENGTH-5 );
795 3 printf("\r\nI2C Write %X", g_UartCommand.Buffer[_UART_CMD_INDEX3_]);
796 3 printf(",%X => ", g_UartCommand.Buffer[_UART_CMD_INDEX4_]);
797 3 for( i = 0; i < UART_CMD_EXT_LENGTH-5; ++ i )
798 3 {
799 4 printf("[%x]", g_UartCommand.Buffer[_UART_CMD_INDEX5_+i]);
800 4 }
801 3 putstr("\r\n");
802 3 break;
803 3 case 0xf1: // I2C Read Bytes(Has sub address)
804 3 i2cBurstReadBytes(g_UartCommand.Buffer[_UART_CMD_INDEX3_],
805 3 g_UartCommand.Buffer[_UART_CMD_INDEX4_],
806 3 acI2cBuf,
807 3 g_UartCommand.Buffer[_UART_CMD_INDEX5_]);
808 3 printf("\r\nI2C Read %x", g_UartCommand.Buffer[_UART_CMD_INDEX3_] );
809 3 printf(",%X => ", g_UartCommand.Buffer[_UART_CMD_INDEX4_] );
810 3 for( i = 0; i < g_UartCommand.Buffer[_UART_CMD_INDEX5_]; ++ i )
811 3 {
812 4 printf("[%x]", acI2cBuf[i]);
813 4 }
814 3 putstr("\r\n");
815 3 break;
816 3 case 0xf2: // I2C Write Bytes(No sub address)
817 3 i2cBurstCurrentBytes( g_UartCommand.Buffer[_UART_CMD_INDEX3_],
818 3 &(g_UartCommand.Buffer[_UART_CMD_INDEX4_]),
819 3 UART_CMD_EXT_LENGTH-4 );
820 3 printf("\r\nI2C Write_2 %X => ", g_UartCommand.Buffer[_UART_CMD_INDEX3_]);
821 3 for( i = 0; i < UART_CMD_EXT_LENGTH-4; ++ i )
822 3 {
823 4 printf("[%x]", g_UartCommand.Buffer[_UART_CMD_INDEX4_+i]);
824 4 }
825 3 putstr("\r\n");
826 3 break;
827 3 case 0xf3: // I2C Read Bytes(No sub address)
828 3 i2cBurstCurrentBytes( g_UartCommand.Buffer[_UART_CMD_INDEX3_],
829 3 acI2cBuf,
830 3 g_UartCommand.Buffer[_UART_CMD_INDEX4_] );
831 3 printf("\r\nI2C Read_2 %x => ", g_UartCommand.Buffer[_UART_CMD_INDEX3_] );
832 3 for( i = 0; i < g_UartCommand.Buffer[_UART_CMD_INDEX4_]; ++ i )
833 3 {
834 4 printf("[%x]", acI2cBuf[i]);
835 4 }
836 3 putstr("\r\n");
837 3 break;
838 3 } // End of switch( device )
839 2 }
840 1 }
841 #endif
842
843 ///////////////////////////////////////
844 // Decode Uart command
845 ///////////////////////////////////////
846 //0 sCALER
847 //1 adc
848 //2 vd
849 //3 COMB
850 //4 ??
851 //5 dsp
852 // OSD
853 //===== ぃノresotre =====
C51 COMPILER V8.01 DEBUG 11/28/2006 08:08:03 PAGE 15
854 //6 MCU
855 //A DEBUG1
856 //B Debug2
857 //C debug3
858 void uartDecodeNormalCommand(void)
859 {
860 1 BYTE ucBank;
861 1
862 1 {
863 2 ucBank = msReadByte(BK0_00_REGBK);
864 2
865 2 switch(UART_CMD)
866 2 {
867 3 /*
868 3 case kEnter_ISP:
869 3 {
870 3 // new check ISP command
871 3 if (g_UartCommand.Buffer[_UART_CMD_INDEX1_] != 0x55 ||
872 3 g_UartCommand.Buffer[_UART_CMD_INDEX2_] != 0xaa)
873 3 break;
874 3
875 3 putstr("\r\n- Isp -");
876 3 #if(PANEL_TYPE_SEL!=PNL_DAC_CRT)
877 3 pwPanelOffSequence();
878 3 #endif
879 3
880 3 #if( MCU_SEL==MCU_W78E65 )
881 3 CHPENR = 0x87; // CHPENR = 0x59, enable CHPCON register write attribute
882 3 CHPENR = 0x59; // CHPENR = 0x59, enable CHPCON register write attribute
883 3 CHPCON = 0x03; // CHPCON = 0x03, enter in-system programming mode
884 3 CHPENR = 0x00; // CHPENR = 0x00, disable CHPCON write attribute
885 3
886 3 TR0 = 0; // Timer0 stop
887 3 IP = 0x00; // Set interrupt priority
888 3
889 3 EA = 1; // Set single interrupt
890 3 ET0 = 1; // Enable TIMER0 iterrrupt
891 3 // Timer0 interrupt enable for wake-up from INDLE mode
892 3
893 3 // Set time for enter ISP mode about 1.676 us
894 3 TL0 = 0xf0; // TL0 = 0xf0
895 3 TH0 = 0xff; // TH0 = 0xff
896 3 TMOD |= 0x01; // Set Timer0 mode 1 (16-bit timer)
897 3 TR0 = 1; // Start Timer0
898 3 PCON = 0x01; // Enter IDLE mode for launching the in-system programmability
899 3 #endif
900 3 #if(MCU_SEL==MCU_W77E532)
901 3 //P4 = 0x00;
902 3
903 3 IE = 0;
904 3 TCON = 0;
905 3
906 3 TA = 0xAA;
907 3 TA = 0x55;
908 3 TURBO_CHPCON = 0x03; // CHPCON = 0x03, enter in-system programming mode
909 3 TA = 0x00;
910 3
911 3 TR0 = 0; // Timer0 stop
912 3 IP = 0x00; // Set interrupt priority
913 3
914 3 EA = 1; // Set single interrupt
915 3 ET0 = 1; // Enable TIMER0 iterrrupt
C51 COMPILER V8.01 DEBUG 11/28/2006 08:08:03 PAGE 16
916 3 // Timer0 interrupt enable for wake-up from INDLE mode
917 3
918 3 // Set time for enter ISP mode about 1.676 us
919 3 TL0 = 0xf0; // TL0 = 0xf0
920 3 TH0 = 0xff; // TH0 = 0xff
921 3 TMOD |= 0x01; // Set Timer0 mode 1 (16-bit timer)
922 3 TR0 = 1; // Start Timer0
923 3 PCON = 0x01; // Enter IDLE mode for launching the in-system programmability
924 3 #endif
925 3 break;
926 3 }
927 3 */
928 3 /*
929 3 case kWrite_MST_Bank0:
930 3 {
931 3 msWriteByte(BK0_00_REGBK, REG_BANK_SCALER);
932 3 msWriteByte(UART_CMD_MS_REG, UART_CMD_MS_DAT);
933 3 if (!g_bDebugASCIICommandFlag) putchar(0xF1);
934 3 break;
935 3 }
936 3 case kRead_MST_Bank0:
937 3 {
938 3 msWriteByte(BK0_00_REGBK, REG_BANK_SCALER);
939 3 UART_CMD_MS_DAT = msReadByte(UART_CMD_MS_REG);
940 3 putchar(0xF2);
941 3 putchar(UART_CMD_MS_DAT);
942 3 if (g_bDebugASCIICommandFlag)
943 3 {
944 3 printf("BK0[0x%x]=", UART_CMD_MS_REG);
945 3 printf("0x%x \r\n", UART_CMD_MS_DAT);
946 3 }
947 3 break;
948 3 }
949 3 case kWrite_MST_Bank1:
950 3 {
951 3 msWriteByte(BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU);
952 3 msWriteByte(UART_CMD_MS_REG, UART_CMD_MS_DAT);
953 3 if (!g_bDebugASCIICommandFlag) putchar(0xF1);
954 3 break;
955 3 }
956 3 case kRead_MST_Bank1:
957 3 {
958 3 msWriteByte(BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU);
959 3 UART_CMD_MS_DAT = msReadByte(UART_CMD_MS_REG);
960 3 putchar(0xF2);
961 3 putchar(UART_CMD_MS_DAT);
962 3 if (g_bDebugASCIICommandFlag)
963 3 {
964 3 printf("BK1[0x%x]=", UART_CMD_MS_REG);
965 3 printf("0x%x \r\n", UART_CMD_MS_DAT);
966 3 }
967 3 break;
968 3 }
969 3 case kWrite_MST_Bank2:
970 3 {
971 3 msWriteByte(BK0_00_REGBK, 2);
972 3 msWriteByte(UART_CMD_MS_REG, UART_CMD_MS_DAT);
973 3 if (!g_bDebugASCIICommandFlag) putchar(0xF1);
974 3 break;
975 3 }
976 3 case kRead_MST_Bank2:
977 3 {
C51 COMPILER V8.01 DEBUG 11/28/2006 08:08:03 PAGE 17
978 3 msWriteByte(BK0_00_REGBK, 2);
979 3 UART_CMD_MS_DAT = msReadByte(UART_CMD_MS_REG);
980 3 putchar(0xF2);
981 3 putchar(UART_CMD_MS_DAT);
982 3 if (g_bDebugASCIICommandFlag)
983 3 {
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