mach64.h

原名叫avifile

/*	?				0x0000f800ul */
#	define DSP_ON			0x07ff0000ul
/*	?				0xf8000000ul */
#define TIMER_CONFIG		BlockIOTag(0x0au)	/* VTB/GTB/LT */
#define MEM_BUF_CNTL		BlockIOTag(0x0bu)	/* VTB/GTB/LT */
#define SHARED_CNTL		BlockIOTag(0x0cu)	/* VTB/GTB/LT */
#define SHARED_MEM_CONFIG	BlockIOTag(0x0du)	/* VTB/GTB/LT */
#define MEM_ADDR_CONFIG		BlockIOTag(0x0du)	/* GTPro */
#define SHARED_CNTL_CTD		BlockIOTag(0x0eu)	/* CTD */
/*	?				0x00fffffful */
#define CTD_FIFO5			0x01000000ul
/*	?				0xfe000000ul */
#define CRT_TRAP		BlockIOTag(0x0eu)	/* VTB/GTB/LT */
#define DSTN_CONTROL		BlockIOTag(0x0fu)	/* LT */
#define I2C_CNTL_0		BlockIOTag(0x0fu)	/* GTPro */
#define OVR_CLR			IOPortTag(0x08u, 0x10u)
#	define OVR_CLR_8		0x000000fful
#	define OVR_CLR_B		0x0000ff00ul
#	define OVR_CLR_G		0x00ff0000ul
#	define OVR_CLR_R		0xff000000ul
#define OVR_WID_LEFT_RIGHT	IOPortTag(0x09u, 0x11u)
#	define OVR_WID_LEFT		0x0000003ful	/* 0x0f on <LT */
/*	?				0x0000ffc0ul */
#	define OVR_WID_RIGHT		0x003f0000ul	/* 0x0f0000 on <LT */
/*	?				0xffc00000ul */
#define OVR_WID_TOP_BOTTOM	IOPortTag(0x0au, 0x12u)
#	define OVR_WID_TOP		0x000001fful	/* 0x00ff on <LT */
/*	?				0x0000fe00ul */
#	define OVR_WID_BOTTOM		0x01ff0000ul	/* 0x00ff0000 on <LT */
/*	?				0xfe000000ul */
#define VGA_DSP_CONFIG		BlockIOTag(0x13u)	/* VTB/GTB/LT */
#	define VGA_DSP_XCLKS_PER_QW	DSP_XCLKS_PER_QW
/*	?				0x000fc000ul */
#	define VGA_DSP_PREC_PCLKBY2	0x00700000ul
/*	?				0x00800000ul */
#	define VGA_DSP_PREC_PCLK	0x07000000ul
/*	?				0xf8000000ul */
#define VGA_DSP_ON_OFF		BlockIOTag(0x14u)	/* VTB/GTB/LT */
#	define VGA_DSP_OFF		DSP_OFF
/*	?				0x0000f800ul */
#	define VGA_DSP_ON		DSP_ON
/*	?				0xf8000000ul */
#define DSP2_CONFIG		BlockIOTag(0x15u)	/* LTPro */
#define DSP2_ON_OFF		BlockIOTag(0x16u)	/* LTPro */
#define EXT_CRTC_GEN_CNTL	BlockIOTag(0x17u)	/* VT-A4 (W) */
#define CRTC2_OFF_PITCH		BlockIOTag(0x17u)	/* LTPro */
#define CUR_CLR0		IOPortTag(0x0bu, 0x18u)
#define CUR_CLR1		IOPortTag(0x0cu, 0x19u)
/* These are for both CUR_CLR0 and CUR_CLR1 */
#	define CUR_CLR_I		0x000000fful
#	define CUR_CLR_B		0x0000ff00ul
#	define CUR_CLR_G		0x00ff0000ul
#	define CUR_CLR_R		0xff000000ul
#	define CUR_CLR			(CUR_CLR_R | CUR_CLR_G | CUR_CLR_B)
#define CUR_OFFSET		IOPortTag(0x0du, 0x1au)
#define CUR_HORZ_VERT_POSN	IOPortTag(0x0eu, 0x1bu)
#	define CUR_HORZ_POSN		0x000007fful
/*	?				0x0000f800ul */
#	define CUR_VERT_POSN		0x07ff0000ul
/*	?				0xf8000000ul */
#define CUR_HORZ_VERT_OFF	IOPortTag(0x0fu, 0x1cu)
#	define CUR_HORZ_OFF		0x0000007ful
/*	?				0x0000ff80ul */
#	define CUR_VERT_OFF		0x007f0000ul
/*	?				0xff800000ul */
#define CONFIG_PANEL		BlockIOTag(0x1du)	/* LT */
#	define PANEL_FORMAT		0x00000007ul
/*	?				0x00000008ul */
#	define PANEL_TYPE		0x000000f0ul
#	define NO_OF_GREY		0x00000700ul
#	define MOD_GEN			0x00001800ul
#	define EXT_LVDS_CLK		0x00001800ul	/* LTPro */
#	define BLINK_RATE		0x00006000ul
#	define BLINK_RATE_PRO		0x00002000ul	/* LTPro */
#	define DONT_SHADOW_HEND		0x00004000ul	/* LTPro */
#	define DONT_USE_F32KHZ		0x00008000ul
#	define LCD_IO_DRIVE		0x00008000ul	/* XC/XL */
#	define FP_POL			0x00010000ul
#	define LP_POL			0x00020000ul
#	define DTMG_POL			0x00040000ul
#	define SCK_POL			0x00080000ul
#	define DITHER_SEL		0x00300000ul
#	define INVERSE_VIDEO_EN		0x00400000ul
#	define BL_CLK_SEL		0x01800000ul
#	define BL_LEVEL			0x0e000000ul
#	define BL_CLK_SEL_PRO		0x00800000ul	/* LTPro */
#	define BL_LEVEL_PRO		0x03000000ul	/* LTPro */
#	define BIAS_LEVEL_PRO		0x0c000000ul	/* LTPro */
#	define HSYNC_DELAY		0xf0000000ul
#define TV_OUT_INDEX		BlockIOTag(0x1du)	/* LTPro */
#	define TV_REG_INDEX		0x000000fful
#	define TV_ON			0x00000100ul
/*	?				0xfffffe00ul */
#define GP_IO			IOPortTag(0x1eu, 0x1eu)	/* VT/GT */
#define GP_IO_CNTL		BlockIOTag(0x1fu)	/* VT/GT */
#define HW_DEBUG		BlockIOTag(0x1fu)	/* VTB/GTB/LT */
#	define FAST_SRCCOPY_DIS		0x00000001ul
#	define BYPASS_SUBPIC_DBF	0x00000001ul	/* XL/XC */
#	define SRC_AUTONA_FIX_DIS	0x00000002ul
#	define SYNC_PD_EN		0x00000002ul	/* Mobility */
#	define DISP_QW_FIX_DIS		0x00000004ul
#	define GUIDST_WB_EXP_DIS	0x00000008ul
#	define CYC_ALL_FIX_DIS		0x00000008ul	/* GTPro */
#	define AGPPLL_FIX_EN		0x00000008ul	/* Mobility */
#	define SRC_AUTONA_ALWAYS_EN	0x00000010ul
#	define GUI_BEATS_HOST_P		0x00000010ul	/* GTPro */
#	define DRV_CNTL_DQMB_WEB	0x00000020ul
#	define FAST_FILL_SCISSOR_DIS	0x00000020ul	/* GT2c/VT4 */
#	define INTER_BLIT_FIX_DIS	0x00000020ul	/* GTPro */
#	define DRV_CNTL_MA		0x00000040ul
#	define AUTO_BLKWRT_COLOR_DIS	0x00000040ul	/* GT2c/VT4 */
#	define INTER_PRIM_DIS		0x00000040ul	/* GTPro */
#	define DRV_CNTL_MD		0x00000080ul
#	define CHG_DEV_ID		0x00000100ul
#	define SRC_TRACK_DST_FIX_DIS	0x00000200ul
#	define HCLK_FB_SKEW		0x00000380ul	/* GT2c/VT4 */
#	define SRC_TRACK_DST_FIX_DIS_P	0x00000080ul	/* GTPro */
#	define AUTO_BLKWRT_COLOR_DIS_P	0x00000100ul	/* GTPro */
#	define INTER_LINE_OVERLAP_DIS	0x00000200ul	/* GTPro */
#	define MEM_OE_PULLBACK		0x00000400ul
#	define DBL_BUFFER_EN		0x00000400ul	/* GTPro */
#	define MEM_WE_FIX_DIS		0x00000800ul
#	define MEM_OE_PULLBACK_B	0x00000800ul	/* GT2c/VT4 */
#	define CMDFIFO_SIZE_DIS_P	0x00000800ul	/* GTPro */
#	define RD_EN_FIX_DIS		0x00001000ul
#	define MEM_WE_FIX_DIS_B		0x00001000ul
#	define AUTO_FF_DIS		0x00001000ul	/* GTPro */
#	define CMDFIFO_SIZE_DIS		0x00002000ul	/* GT2c/VT4 */
#	define AUTO_BLKWRT_DIS		0x00002000ul	/* GTPro */
#	define GUI_BEATS_HOST		0x00004000ul	/* GT2c/VT4 */
#	define ORED_INVLD_RB_CACHE	0x00004000ul	/* GTPro */
#	define BLOCK_DBL_BUF		0x00008000ul	/* GTPro */
#	define R2W_TURNAROUND_DELAY	0x00020000ul	/* GT2c/VT4 */
#	define ENA_32BIT_DATA_BUS	0x00040000ul	/* GT2c/VT4 */
#	define HCLK_FB_SKEW_P		0x00070000ul	/* GTPro */
#	define ENA_FLASH_ROM		0x00080000ul	/* GT2c/VT4 */
#	define DISABLE_SWITCH_FIX	0x00080000ul	/* GTPro */
#	define MCLK_START_EN		0x00080000ul	/* LTPro */
#	define SEL_VBLANK_BDL_BUF	0x00100000ul	/* GTPro */
#	define CMDFIFO_64EN		0x00200000ul	/* GTPro must be set if IDCT_EN */
#	define BM_FIX_DIS		0x00400000ul	/* GTPro */
#	define Z_SWITCH_EN		0x00800000ul	/* LTPro */
#	define FLUSH_HOST_WB		0x01000000ul	/* GTPro */
#	define HW_DEBUG_WRITE_MSK_FIX_DIS	0x02000000ul	/* LTPro */
#	define Z_NO_WRITE_EN		0x04000000ul	/* LTPro */
#	define DISABLE_PCLK_RESET_P	0x08000000ul	/* LTPro */
#	define PM_D3_SUPPORT_ENABLE_P	0x10000000ul	/* LTPro */
#	define STARTCYCLE_FIX_ENABLE	0x20000000ul	/* LTPro */
#	define DONT_RST_CHAREN		0x20000000ul	/* XL/XC */
#	define C3_FIX_ENABLE		0x40000000ul	/* LTPro */
#	define BM_HOSTRA_EN		0x40000000ul	/* XL/XC */
#	define PKGBGAb			0x80000000ul	/* XL/XC */
#	define AUTOEXP_HORZ_FIX		0x80000000ul	/* Mobility */
#define SCRATCH_REG0		IOPortTag(0x10u, 0x20u)
#define SCRATCH_REG1		IOPortTag(0x11u, 0x21u)
/*	BIOS_BASE_SEGMENT		0x0000007ful */	/* As above */
/*	?				0x00000f80ul */
#define BIOS_INIT_DAC_SUBTYPE		0x0000f000ul
/*	?				0xffff0000ul */
#define SCRATCH_REG2		BlockIOTag(0x22u)	/* LT */
#define SCRATCH_REG3		BlockIOTag(0x23u)	/* GTPro */
#define CLOCK_CNTL		IOPortTag(0x12u, 0x24u)
#	define CLOCK_BIT		0x00000004ul	/* For ICS2595 */
#	define CLOCK_PULSE		0x00000008ul	/* For ICS2595 */
#	define CLOCK_SELECT		0x0000000ful
#	define CLOCK_DIVIDER		0x00000030ul
#	define CLOCK_STROBE		0x00000040ul
#	define CLOCK_DATA		0x00000080ul
/*	?				0x00000100ul */
#	define PLL_WR_EN		0x00000200ul	/* For internal PLL */
#	define PLL_ADDR			0x0000fc00ul	/* For internal PLL */
#	define PLL_DATA			0x00ff0000ul	/* For internal PLL */
/*	?				0xff000000ul */
#define CONFIG_STAT64_1		BlockIOTag(0x25u)	/* GTPro */
#	define CFG_SUBSYS_DEV_ID	0x000000fful
#	define CFG_SUBSYS_VEN_ID	0x00ffff00ul
/*	?				0x1f000000ul */
#	define CFG_DIMM_TYPE		0xe0000000ul
#	define CFG_PCI_SUBSYS_DEV_ID	0x0000fffful	/* XC/XL */
#	define CFG_PCI_SUBSYS_VEN_ID	0xffff0000ul	/* XC/XL */
#define CONFIG_STAT64_2		BlockIOTag(0x26u)	/* GTPro */
#	define CFG_DIMM_TYPE_3		0x00000001ul
/*	?				0x0000001eul */
#	define CFG_ROMWRTEN		0x00000020ul
#	define CFG_AGPVCOGAIN		0x000000c0ul
#	define CFG_PCI_TYPE		0x00000100ul
#	define CFG_AGPSKEW		0x00000e00ul
#	define CFG_X1CLKSKEW		0x00007000ul
#	define CFG_PANEL_ID_P		0x000f8000ul	/* LTPro */
/*	?				0x00100000ul */
#	define CFG_PREFETCH_EN		0x00200000ul
#	define CFG_ID_DISABLE		0x00400000ul
#	define CFG_PRE_TESTEN		0x00800000ul
/*	?				0x01000000ul */
#	define CFG_PCI5VEN		0x02000000ul	/* LTPro */
#	define CFG_VGA_DISABLE		0x04000000ul
#	define CFG_ENINTB		0x08000000ul
/*	?				0x10000000ul */
#	define CFG_ROM_REMAP_2		0x20000000ul
#	define CFG_IDSEL		0x40000000ul
/*	?				0x80000000ul */
#define TV_OUT_DATA		BlockIOTag(0x27u)	/* LTPro */
#define BUS_CNTL		IOPortTag(0x13u, 0x28u)
#	define BUS_WS			0x0000000ful
#	define BUS_DBL_RESYNC		0x00000001ul	/* VTB/GTB/LT */
#	define BUS_MSTR_RESET		0x00000002ul	/* VTB/GTB/LT */
#	define BUS_FLUSH_BUF		0x00000004ul	/* VTB/GTB/LT */
#	define BUS_STOP_REQ_DIS		0x00000008ul	/* VTB/GTB/LT */
#	define BUS_ROM_WS		0x000000f0ul
#	define BUS_APER_REG_DIS		0x00000010ul	/* VTB/GTB/LT */
#	define BUS_EXTRA_PIPE_DIS	0x00000020ul	/* VTB/GTB/LT */
#	define BUS_MASTER_DIS		0x00000040ul	/* VTB/GTB/LT */
#	define BUS_ROM_WRT_EN		0x00000080ul	/* GTPro */
#	define BUS_ROM_PAGE		0x00000f00ul
#	define BUS_MINOR_REV_ID		0x00000700ul	/* LTPro */
#	define BUS_EXT_REG_EN		0x08000000ul
/*		First silicom - Prototype (A11)	0x00000000ul */
/*		Metal mask spin (A12 & A13)	0x00000100ul */
/*		All layer spin (A21)		0x00000200ul */
/*		Fast metal spin (A22) - Prod.	0x00000300ul */
/*		All layer spin (A31)		0x00000700ul */
/*	?				0x00000800ul */	/* LTPro */
#	define BUS_CHIP_HIDDEN_REV	0x00000300ul	/* XC/XL */
/*	?				0x00001c00ul */	/* XC/XL */
#	define BUS_ROM_DIS		0x00001000ul
#	define BUS_IO_16_EN		0x00002000ul	/* GX */
#	define BUS_PCI_READ_RETRY_EN	0x00002000ul	/* VTB/GTB/LT */
#	define BUS_DAC_SNOOP_EN		0x00004000ul
#	define BUS_PCI_RETRY_EN		0x00008000ul	/* VT/GT */
#	define BUS_PCI_WRT_RETRY_EN	0x00008000ul	/* VTB/GTB/LT */
#	define BUS_FIFO_WS		0x000f0000ul
#	define BUS_RETRY_WS		0x000f0000ul	/* VTB/GTB/LT */
#	define BUS_FIFO_ERR_INT_EN	0x00100000ul
#	define BUS_MSTR_RD_MULT		0x00100000ul	/* VTB/GTB/LT */
#	define BUS_FIFO_ERR_INT		0x00200000ul
#	define BUS_MSTR_RD_LINE		0x00200000ul	/* VTB/GTB/LT */
#	define BUS_HOST_ERR_INT_EN	0x00400000ul
#	define BUS_SUSPEND		0x00400000ul	/* GTPro */
#	define BUS_HOST_ERR_INT		0x00800000ul
#	define BUS_LAT16X		0x00800000ul	/* GTPro */
#	define BUS_PCI_DAC_WS		0x07000000ul
#	define BUS_RD_DISCARD_EN	0x01000000ul	/* VTB/GTB/LT */
#	define BUS_RD_ABORT_EN		0x02000000ul	/* VTB/GTB/LT */
#	define BUS_MSTR_WS		0x04000000ul	/* VTB/GTB/LT */
#	define BUS_PCI_DAC_DLY		0x08000000ul
#	define BUS_EXT_REG_EN		0x08000000ul	/* VT/GT */
#	define BUS_PCI_MEMW_WS		0x10000000ul
#	define BUS_MSTR_DISCONNECT_EN	0x10000000ul	/* VTB/GTB/LT */
#	define BUS_PCI_BURST_DEC	0x20000000ul	/* GX/CX */
#	define BUS_BURST		0x20000000ul	/* 264xT */
#	define BUS_WRT_BURST		0x20000000ul	/* VTB/GTB/LT */
#	define BUS_RDY_READ_DLY		0xc0000000ul
#	define BUS_READ_BURST		0x40000000ul	/* VTB/GTB/LT */
#	define BUS_RDY_READ_DLY_B	0x80000000ul	/* VTB/GTB/LT */
#define LCD_INDEX		BlockIOTag(0x29u)	/* LTPro */
#	define LCD_REG_INDEX		0x0000003ful
#	define LCD_DISPLAY_DIS		0x00000100ul
#	define LCD_SRC_SEL		0x00000200ul
#	define LCD_SRC_SEL_CRTC1	0x00000000ul
#	define LCD_SRC_SEL_CRTC2	0x00000200ul
#	define LCD_CRTC2_DISPLAY_DIS	0x00000400ul
#	define LCD_GUI_ACTIVE		0x00000800ul	/* XC/XL */
#	define LCD_MONDET_SENSE		0x01000000ul	/* XC/XL */
#	define LCD_MONDET_INT_POL	0x02000000ul	/* XC/XL */
#	define LCD_MONDET_INT_EN	0x04000000ul	/* XC/XL */
#	define LCD_MONDET_INT		0x08000000ul	/* XC/XL */
#	define LCD_MONDET_EN		0x10000000ul	/* XC/XL */
#	define LCD_EN_PL		0x20000000ul	/* XC/XL */
#define HFB_PITCH_ADDR		BlockIOTag(0x2au)	/* LT */
#define LCD_DATA		BlockIOTag(0x2au)	/* LTPro */
#define EXT_MEM_CNTL		BlockIOTag(0x2bu)	/* VTB/GTB/LT */
#define MEM_CNTL		IOPortTag(0x14u, 0x2cu)
#	define CTL_MEM_SIZE		0x00000007ul
/*	?				0x00000008ul */
#	define CTL_MEM_REFRESH		0x00000078ul	/* VT/GT */
#	define CTL_MEM_SIZEB		0x0000000ful	/* VTB/GTB/LT */
#	define CTL_MEM_RD_LATCH_EN	0x00000010ul
#	define CTL_MEM_RD_LATCH_DLY	0x00000020ul
#	define CTL_MEM_LATENCY		0x00000030ul	/* VTB/GTB/LT */
#	define CTL_MEM_SD_LATCH_EN	0x00000040ul
#	define CTL_MEM_SD_LATCH_DLY	0x00000080ul
#	define CTL_MEM_LATCH		0x000000c0ul	/* VTB/GTB/LT */
#	define CTL_MEM_WDOE_CNTL	0x000000c0ul	/* XC/XL */
#	define CTL_MEM_FULL_PLS		0x00000100ul
#	define CTL_MEM_CYC_LNTH_AUX	0x00000180ul	/* VT/GT */
#	define CTL_MEM_TRP		0x00000300ul	/* VTB/GTB/LT */
#	define CTL_MEM_CYC_LNTH		0x00000600ul
#	define CTL_MEM_REFRESH_RATE	0x00001800ul	/* 264xT */
#	define CTL_MEM_TRCD		0x00000c00ul	/* VTB/GTB/LT */
#	define CTL_MEM_WR_RDY_SEL	0x00000800ul	/* GX/CX */
#	define CTL_MEM_EXT_RMW_CYC_EN	0x00001000ul	/* GX/CX */
#	define CTL_MEM_TCRD		0x00001000ul	/* VTB/GTB/LT */
#	define CTL_MEM_DLL_RESET	0x00002000ul	/* VT/GT */
#	define CTL_MEM_TR2W		0x00002000ul	/* GTPro */
#	define CTL_MEM_ACTV_PRE		0x0000c000ul	/* VT/GT */
#	define CTL_MEM_CAS_PHASE	0x00004000ul	/* GTPro */
#	define CTL_MEM_OE_PULLBACK	0x00008000ul	/* GTPro */
#	define CTL_MEM_TWR		0x0000c000ul	/* XC/XL */
#	define CTL_MEM_BNDRY		0x00030000ul
#	define CTL_MEM_BNDRY_0K		0x00000000ul
#	define CTL_MEM_BNDRY_256K	0x00010000ul
#	define CTL_MEM_BNDRY_512K	0x00020000ul
#	define CTL_MEM_BNDRY_1024K	0x00030000ul
#	define CTL_MEM_DLL_GAIN_CNTL	0x00030000ul	/* VT/GT */
#	define CTL_MEM_BNDRY_EN		0x00040000ul
#	define CTL_MEM_SDRAM_RESET	0x00040000ul	/* VT/GT */
#	define CTL_MEM_TRAS		0x00070000ul	/* VTB/GTB/LT */
#	define CTL_MEM_TILE_SELECT	0x00180000ul	/* VT/GT */
#	define CTL_MEM_REFRESH_DIS	0x00080000ul	/* VTB/GTB/LT */
#	define CTL_MEM_LOW_LATENCY_MODE	0x00200000ul	/* VT/GT */
#	define CTL_MEM_CDE_PULLBACK	0x00400000ul	/* VT/GT */
#	define CTL_MEM_REFRESH_RATE_B	0x00f00000ul	/* VTB/GTB/LT */
#	define CTL_MEM_PIX_WIDTH	0x07000000ul
#	define CTL_MEM_LOWER_APER_ENDIAN	0x03000000ul	/* VTB/GTB/LT */
#	define CTL_MEM_OE_SELECT	0x18000000ul	/* VT/GT */
#	define CTL_MEM_UPPER_APER_ENDIAN	0x0c000000ul	/* VTB/GTB/LT */
/*	?				0xe0000000ul */
#	define CTL_MEM_PAGE_SIZE	0x30000000ul	/* VTB/GTB/LT */
#define MEM_VGA_WP_SEL		IOPortTag(0x15u, 0x2du)
#	define MEM_VGA_WPS0		0x0000fffful
#	define MEM_VGA_WPS1		0xffff0000ul
#define MEM_VGA_RP_SEL		IOPortTag(0x16u, 0x2eu)