radeon.h

原名叫avifile

#	define DST_Y_TOP_TO_BOTTOM		0x00000002
#	define DST_X_MAJOR			0x00000000
#	define DST_Y_MAJOR			0x00000004
#	define DST_X_TILE			0x00000008
#	define DST_Y_TILE			0x00000010
#	define DST_LAST_PEL			0x00000020
#	define DST_TRAIL_X_RIGHT_TO_LEFT	0x00000000
#	define DST_TRAIL_X_LEFT_TO_RIGHT	0x00000040
#	define DST_TRAP_FILL_RIGHT_TO_LEFT	0x00000000
#	define DST_TRAP_FILL_LEFT_TO_RIGHT	0x00000080
#	define DST_BRES_SIGN			0x00000100
#	define DST_HOST_BIG_ENDIAN_EN		0x00000200
#	define DST_POLYLINE_NONLAST		0x00008000
#	define DST_RASTER_STALL			0x00010000
#	define DST_POLY_EDGE			0x00040000
#define	DP_CNTL_XDIR_YDIR_YMAJOR		0x16D0
/* DP_CNTL_XDIR_YDIR_YMAJOR bit	constants (short version of DP_CNTL) */
#	define DST_X_MAJOR_S			0x00000000
#	define DST_Y_MAJOR_S			0x00000001
#	define DST_Y_BOTTOM_TO_TOP_S		0x00000000
#	define DST_Y_TOP_TO_BOTTOM_S		0x00008000
#	define DST_X_RIGHT_TO_LEFT_S		0x00000000
#	define DST_X_LEFT_TO_RIGHT_S		0x80000000
#define	DP_DATATYPE				0x16C4
/* DP_DATATYPE bit constants */
#	define DST_8BPP				0x00000002
#	define DST_15BPP			0x00000003
#	define DST_16BPP			0x00000004
#	define DST_24BPP			0x00000005
#	define DST_32BPP			0x00000006
#	define DST_8BPP_RGB332			0x00000007
#	define DST_8BPP_Y8			0x00000008
#	define DST_8BPP_RGB8			0x00000009
#	define DST_16BPP_VYUY422		0x0000000b
#	define DST_16BPP_YVYU422		0x0000000c
#	define DST_32BPP_AYUV444		0x0000000e
#	define DST_16BPP_ARGB4444		0x0000000f
#	define BRUSH_SOLIDCOLOR			0x00000d00
#	define SRC_MONO				0x00000000
#	define SRC_MONO_LBKGD			0x00010000
#	define SRC_DSTCOLOR			0x00030000
#	define BYTE_ORDER_MSB_TO_LSB		0x00000000
#	define BYTE_ORDER_LSB_TO_MSB		0x40000000
#	define DP_CONVERSION_TEMP		0x80000000
#	define HOST_BIG_ENDIAN_EN		(1 << 29)
#define	DP_MIX					0x16C8
/* DP_MIX bit constants	*/
#	define DP_SRC_RECT			0x00000200
#	define DP_SRC_HOST			0x00000300
#	define DP_SRC_HOST_BYTEALIGN		0x00000400
#define	DP_WRITE_MSK				0x16CC
#define	DP_XOP					0x17F8
#define	CLR_CMP_CLR_SRC				0x15C4
#define	CLR_CMP_CLR_DST				0x15C8
#define	CLR_CMP_CNTL				0x15C0
/* CLR_CMP_CNTL	bit constants */
#	define COMPARE_SRC_FALSE		0x00000000
#	define COMPARE_SRC_TRUE			0x00000001
#	define COMPARE_SRC_NOT_EQUAL		0x00000004
#	define COMPARE_SRC_EQUAL		0x00000005
#	define COMPARE_SRC_EQUAL_FLIP		0x00000007
#	define COMPARE_DST_FALSE		0x00000000
#	define COMPARE_DST_TRUE			0x00000100
#	define COMPARE_DST_NOT_EQUAL		0x00000400
#	define COMPARE_DST_EQUAL		0x00000500
#	define COMPARE_DESTINATION		0x00000000
#	define COMPARE_SOURCE			0x01000000
#	define COMPARE_SRC_AND_DST		0x02000000
#define	CLR_CMP_MSK				0x15CC
#define	DSTCACHE_MODE				0x1710
#define	DSTCACHE_CTLSTAT			0x1714
/* DSTCACHE_CTLSTAT bit	constants */
#	define RB2D_DC_FLUSH			(3 << 0)
#	define RB2D_DC_FLUSH_ALL		0xf
#	define RB2D_DC_BUSY			(1 << 31)
#define	DEFAULT_OFFSET				0x16e0
#define	DEFAULT_PITCH_OFFSET			0x16E0
#define	DEFAULT_SC_BOTTOM_RIGHT			0x16E8
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
#	define DEFAULT_SC_RIGHT_MAX		(0x1fff	<< 0)
#	define DEFAULT_SC_BOTTOM_MAX		(0x1fff	<< 16)
#define	DP_GUI_MASTER_CNTL			0x146C
/* DP_GUI_MASTER_CNTL bit constants */
#	define GMC_SRC_PITCH_OFFSET_DEFAULT	0x00000000
#	define GMC_SRC_PITCH_OFFSET_LEAVE	0x00000001
#	define GMC_DST_PITCH_OFFSET_DEFAULT	0x00000000
#	define GMC_DST_PITCH_OFFSET_LEAVE	0x00000002
#	define GMC_SRC_CLIP_DEFAULT		0x00000000
#	define GMC_SRC_CLIP_LEAVE		0x00000004
#	define GMC_DST_CLIP_DEFAULT		0x00000000
#	define GMC_DST_CLIP_LEAVE		0x00000008
#	define GMC_BRUSH_8x8MONO		0x00000000
#	define GMC_BRUSH_8x8MONO_LBKGD		0x00000010
#	define GMC_BRUSH_8x1MONO		0x00000020
#	define GMC_BRUSH_8x1MONO_LBKGD		0x00000030
#	define GMC_BRUSH_1x8MONO		0x00000040
#	define GMC_BRUSH_1x8MONO_LBKGD		0x00000050
#	define GMC_BRUSH_32x1MONO		0x00000060
#	define GMC_BRUSH_32x1MONO_LBKGD		0x00000070
#	define GMC_BRUSH_32x32MONO		0x00000080
#	define GMC_BRUSH_32x32MONO_LBKGD	0x00000090
#	define GMC_BRUSH_8x8COLOR		0x000000a0
#	define GMC_BRUSH_8x1COLOR		0x000000b0
#	define GMC_BRUSH_1x8COLOR		0x000000c0
#	define GMC_BRUSH_SOLID_COLOR		0x000000d0
#	define GMC_DST_8BPP			0x00000200
#	define GMC_DST_15BPP			0x00000300
#	define GMC_DST_16BPP			0x00000400
#	define GMC_DST_24BPP			0x00000500
#	define GMC_DST_32BPP			0x00000600
#	define GMC_DST_8BPP_RGB332		0x00000700
#	define GMC_DST_8BPP_Y8			0x00000800
#	define GMC_DST_8BPP_RGB8		0x00000900
#	define GMC_DST_16BPP_VYUY422		0x00000b00
#	define GMC_DST_16BPP_YVYU422		0x00000c00
#	define GMC_DST_32BPP_AYUV444		0x00000e00
#	define GMC_DST_16BPP_ARGB4444		0x00000f00
#	define GMC_SRC_MONO			0x00000000
#	define GMC_SRC_MONO_LBKGD		0x00001000
#	define GMC_SRC_DSTCOLOR			0x00003000
#	define GMC_BYTE_ORDER_MSB_TO_LSB	0x00000000
#	define GMC_BYTE_ORDER_LSB_TO_MSB	0x00004000
#	define GMC_DP_CONVERSION_TEMP_9300	0x00008000
#	define GMC_DP_CONVERSION_TEMP_6500	0x00000000
#	define GMC_DP_SRC_RECT			0x02000000
#	define GMC_DP_SRC_HOST			0x03000000
#	define GMC_DP_SRC_HOST_BYTEALIGN	0x04000000
#	define GMC_3D_FCN_EN_CLR		0x00000000
#	define GMC_3D_FCN_EN_SET		0x08000000
#	define GMC_DST_CLR_CMP_FCN_LEAVE	0x00000000
#	define GMC_DST_CLR_CMP_FCN_CLEAR	0x10000000
#	define GMC_AUX_CLIP_LEAVE		0x00000000
#	define GMC_AUX_CLIP_CLEAR		0x20000000
#	define GMC_WRITE_MASK_LEAVE		0x00000000
#	define GMC_WRITE_MASK_SET		0x40000000
#	define GMC_CLR_CMP_CNTL_DIS		(1 << 28)
#	define GMC_SRC_DATATYPE_COLOR		(3 << 12)
#	define ROP3_S				0x00cc0000
#	define ROP3_SRCCOPY			0x00cc0000
#	define ROP3_P				0x00f00000
#	define ROP3_PATCOPY			0x00f00000
#	define DP_SRC_SOURCE_MASK		(7    << 24)
#	define GMC_BRUSH_NONE			(15   <<  4)
#	define DP_SRC_SOURCE_MEMORY		(2    << 24)
#	define GMC_BRUSH_SOLIDCOLOR		0x000000d0
#define	SC_TOP_LEFT				0x16EC
#define	SC_BOTTOM_RIGHT				0x16F0
#define	SRC_SC_BOTTOM_RIGHT			0x16F4
#define	RB2D_DSTCACHE_CTLSTAT			0x342C
#define	RB2D_DSTCACHE_MODE			0x3428

#define	BASE_CODE				0x0f0b/*0x0f08*/
#define	RADEON_BIOS_0_SCRATCH			0x0010
#define	RADEON_BIOS_1_SCRATCH			0x0014
#define	RADEON_BIOS_2_SCRATCH			0x0018
#define	RADEON_BIOS_3_SCRATCH			0x001c
#define	RADEON_BIOS_4_SCRATCH			0x0020
#define	RADEON_BIOS_5_SCRATCH			0x0024
#define	RADEON_BIOS_6_SCRATCH			0x0028
#define	RADEON_BIOS_7_SCRATCH			0x002c


#define	CLK_PIN_CNTL				0x0001
#define	PPLL_CNTL				0x0002
#	define PPLL_RESET			(1 <<  0)
#	define PPLL_SLEEP			(1 <<  1)
#	define PPLL_ATOMIC_UPDATE_EN		(1 << 16)
#	define PPLL_VGA_ATOMIC_UPDATE_EN	(1 << 17)
#	define PPLL_ATOMIC_UPDATE_VSYNC		(1 << 18)
#define	PPLL_REF_DIV				0x0003
#	define PPLL_REF_DIV_MASK		0x03ff
#	define PPLL_ATOMIC_UPDATE_R		(1 << 15) /* same as _W */
#	define PPLL_ATOMIC_UPDATE_W		(1 << 15) /* same as _R */
#define	PPLL_DIV_0				0x0004
#define	PPLL_DIV_1				0x0005
#define	PPLL_DIV_2				0x0006
#define	PPLL_DIV_3				0x0007
#define	VCLK_ECP_CNTL				0x0008
#	define VCLK_SRC_SEL_MASK		0x03
#	define VCLK_SRC_SEL_CPUCLK		0x00
#	define VCLK_SRC_SEL_PSCANCLK		0x01
#	define VCLK_SRC_SEL_BYTECLK		0x02
#	define VCLK_SRC_SEL_PPLLCLK		0x03
#define	HTOTAL_CNTL				0x0009
#define	HTOTAL2_CNTL				0x002e /* PLL */
#define	M_SPLL_REF_FB_DIV			0x000a
#define	AGP_PLL_CNTL				0x000b
#define	SPLL_CNTL				0x000c
#define	SCLK_CNTL				0x000d
#	define DYN_STOP_LAT_MASK		0x00007ff8
#	define CP_MAX_DYN_STOP_LAT		0x0008
#	define SCLK_FORCEON_MASK		0xffff8000
#define SCLK_MORE_CNTL				0x0035 /* PLL */
#	define SCLK_MORE_FORCEON		0x0700
#define	MPLL_CNTL				0x000e
#ifdef RAGE128
#define MCLK_CNTL				0x000f /* PLL */
#	define FORCE_GCP			(1 << 16)
#	define FORCE_PIPE3D_CP			(1 << 17)
#	define FORCE_RCP			(1 << 18)
#else
#define	MCLK_CNTL				0x0012
/* MCLK_CNTL bit constants */
#	define FORCEON_MCLKA			(1 << 16)
#	define FORCEON_MCLKB			(1 << 17)
#	define FORCEON_YCLKA			(1 << 18)
#	define FORCEON_YCLKB			(1 << 19)
#	define FORCEON_MC			(1 << 20)
#	define FORCEON_AIC			(1 << 21)
#endif
#define	PLL_TEST_CNTL				0x0013
#define	P2PLL_CNTL				0x002a /* P2PLL	*/
#	define P2PLL_RESET			(1 <<  0)
#	define P2PLL_SLEEP			(1 <<  1)
#	define P2PLL_ATOMIC_UPDATE_EN		(1 << 16)
#	define P2PLL_VGA_ATOMIC_UPDATE_EN	(1 << 17)
#	define P2PLL_ATOMIC_UPDATE_VSYNC	(1 << 18)
#define	P2PLL_DIV_0				0x002c
#	define P2PLL_FB0_DIV_MASK		0x07ff
#	define P2PLL_POST0_DIV_MASK		0x00070000
#define	P2PLL_REF_DIV				0x002B /* PLL */
#	define P2PLL_REF_DIV_MASK		0x03ff
#	define P2PLL_ATOMIC_UPDATE_R		(1 << 15) /* same as _W */
#	define P2PLL_ATOMIC_UPDATE_W		(1 << 15) /* same as _R */
#define PIXCLKS_CNTL				0x002d
#	define PIX2CLK_SRC_SEL_MASK		0x03
#	define PIX2CLK_SRC_SEL_CPUCLK		0x00
#	define PIX2CLK_SRC_SEL_PSCANCLK		0x01
#	define PIX2CLK_SRC_SEL_BYTECLK		0x02
#	define PIX2CLK_SRC_SEL_P2PLLCLK		0x03

/* masks */

#define	CONFIG_MEMSIZE_MASK		0x1f000000
#define	MEM_CFG_TYPE			0x40000000
#define	DST_OFFSET_MASK			0x003fffff
#define	DST_PITCH_MASK			0x3fc00000
#define	DEFAULT_TILE_MASK		0xc0000000
#define	PPLL_DIV_SEL_MASK		0x00000300
#define	PPLL_FB3_DIV_MASK		0x000007ff
#define	PPLL_POST3_DIV_MASK		0x00070000

/* BUS MASTERING */
#ifdef RAGE128
#define BM_FRAME_BUF_OFFSET			0xA00
#define BM_SYSTEM_MEM_ADDR			0xA04
#define BM_COMMAND				0xA08
#	define BM_INTERRUPT_DIS			0x08000000
#	define BM_TRANSFER_DEST_REG		0x10000000
#	define BM_FORCE_TO_PCI			0x20000000
#	define BM_FRAME_OFFSET_HOLD		0x40000000
#	define BM_END_OF_LIST			0x80000000
#define BM_STATUS				0xA0c
#define BM_QUEUE_STATUS				0xA10
#define BM_QUEUE_FREE_STATUS			0xA14
#define BM_CHUNK_0_VAL				0xA18
#	define BM_PTR_FORCE_TO_PCI		0x00200000
#	define BM_PM4_RD_FORCE_TO_PCI		0x00400000
#	define BM_GLOBAL_FORCE_TO_PCI		0x00800000
#	define BM_VIP3_NOCHUNK			0x10000000
#	define BM_VIP2_NOCHUNK			0x20000000
#	define BM_VIP1_NOCHUNK			0x40000000
#	define BM_VIP0_NOCHUNK			0x80000000
#define BM_CHUNK_1_VAL				0xA1C
#define BM_VIP0_BUF				0xA20
#	define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO	0x0
#	define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM	0x1
#define BM_VIP0_ACTIVE				0xA24
#define BM_VIP1_BUF				0xA30
#define BM_VIP1_ACTIVE				0xA34
#define BM_VIP2_BUF				0xA40
#define BM_VIP2_ACTIVE				0xA44
#define BM_VIP3_BUF				0xA50
#define BM_VIP3_ACTIVE				0xA54
#define BM_VIDCAP_BUF0				0xA60
#define BM_VIDCAP_BUF1				0xA64
#define BM_VIDCAP_BUF2				0xA68
#define BM_VIDCAP_ACTIVE			0xA6c
#define BM_GUI					0xA80
#define BM_ABORT				0xA88
#endif
/* RAGE	THEATER	REGISTERS */

#define DMA_VIPH0_COMMAND			0x0A00
#define DMA_VIPH1_COMMAND			0x0A04
#define DMA_VIPH2_COMMAND			0x0A08
#define DMA_VIPH3_COMMAND			0x0A0C
#define DMA_VIPH_STATUS				0x0A10
#define DMA_VIPH_CHUNK_0			0x0A18
#define DMA_VIPH_CHUNK_1_VAL			0x0A1C
#define DMA_VIP0_TABLE_ADDR			0x0A20
#define DMA_VIPH0_ACTIVE			0x0A24
#define DMA_VIP1_TABLE_ADDR			0x0A30
#define DMA_VIPH1_ACTIVE			0x0A34
#define DMA_VIP2_TABLE_ADDR			0x0A40
#define DMA_VIPH2_ACTIVE			0x0A44
#define DMA_VIP3_TABLE_ADDR			0x0A50
#define DMA_VIPH3_ACTIVE			0x0A54
#define DMA_VIPH_ABORT				0x0A88

#define	VIPH_CH0_DATA				0x0c00
#define	VIPH_CH1_DATA				0x0c04
#define	VIPH_CH2_DATA				0x0c08
#define	VIPH_CH3_DATA				0x0c0c
#define	VIPH_CH0_ADDR				0x0c10
#define	VIPH_CH1_ADDR				0x0c14
#define	VIPH_CH2_ADDR				0x0c18
#define	VIPH_CH3_ADDR				0x0c1c
#define	VIPH_CH0_SBCNT				0x0c20
#define	VIPH_CH1_SBCNT				0x0c24
#define	VIPH_CH2_SBCNT				0x0c28
#define	VIPH_CH3_SBCNT				0x0c2c
#define	VIPH_CH0_ABCNT				0x0c30
#define	VIPH_CH1_ABCNT				0x0c34
#define	VIPH_CH2_ABCNT				0x0c38
#define	VIPH_CH3_ABCNT				0x0c3c
#define	VIPH_CONTROL				0x0c40
#define	VIPH_DV_LAT				0x0c44
#define	VIPH_BM_CHUNK				0x0c48
#define	VIPH_DV_INT				0x0c4c
#define	VIPH_TIMEOUT_STAT			0x0c50

#define	VIPH_REG_DATA				0x0084
#define	VIPH_REG_ADDR				0x0080

/* Address Space Rage Theatre Registers	(VIP Access) */
#define	VIP_VIP_VENDOR_DEVICE_ID		0x0000
#define	VIP_VIP_SUB_VENDOR_DEVICE_ID		0x0004
#define	VIP_VIP_COMMAND_STATUS			0x0008
#define	VIP_VIP_REVISION_ID			0x000c
#define	VIP_HW_DEBUG				0x0010
#define	VIP_SW_SCRATCH				0x0014
#define	VIP_I2C_CNTL_0				0x0020
#define	VIP_I2C_CNTL_1				0x0024
#define	VIP_I2C_DATA				0x0028
#define	VIP_INT_CNTL				0x002c
#define	VIP_GPIO_INOUT				0x0030
#define	VIP_GPIO_CNTL				0x0034
#define	VIP_CLKOUT_GPIO_CNTL			0x0038
#define	VIP_RIPINTF_PORT_CNTL			0x003c
#define	VIP_ADC_CNTL				0x0400
#define	VIP_ADC_DEBUG				0x0404
#define	VIP_STANDARD_SELECT			0x0408
#define	VIP_THERMO2BIN_STATUS			0x040c
#define	VIP_COMB_CNTL0				0x0440
#define	VIP_COMB_CNTL1				0x0444
#define	VIP_COMB_CNTL2				0x0448
#define	VIP_COMB_LINE_LENGTH			0x044c
#define	VIP_NOISE_CNTL0				0x0450
#define	VIP_HS_PLINE				0x0480
#define	VIP_HS_DTOINC				0x0484
#define	VIP_HS_PLLGAIN				0x0488
#define	VIP_HS_MINMAXWIDTH			0x048c
#define	VIP_HS_GENLOCKDELAY			0x0490
#define	VIP_HS_WINDOW_LIMIT			0x0494
#define	VIP_HS_WINDOW_OC_SPEED			0x0498
#define	VIP_HS_PULSE_WIDTH			0x049c
#define	VIP_HS_PLL_ERROR			0x04a0
#define	VIP_HS_PLL_FS_PATH			0x04a4
#define	VIP_SG_BLACK_GATE			0x04c0
#define	VIP_SG_SYNCTIP_GATE			0x04c4
#define	VIP_SG_UVGATE_GATE			0x04c8
#define	VIP_LP_AGC_CLAMP_CNTL0			0x0500
#define	VIP_LP_AGC_CLAMP_CNTL1			0x0504
#define	VIP_LP_BRIGHTNESS			0x0508
#define	VIP_LP_CONTRAST				0x050c
#define	VIP_LP_SLICE_LIMIT			0x0510
#define	VIP_LP_WPA_CNTL0			0x0514
#define	VIP_LP_WPA_CNTL1			0x0518
#define	VIP_LP_BLACK_LEVEL			0x051c
#define	VIP_LP_SLICE_LEVEL			0x0520
#define	VIP_LP_SYNCTIP_LEVEL			0x0524
#define	VIP_LP_VERT_LOCKOUT			0x0528
#define	VIP_VS_DETECTOR_CNTL			0x0540
#define	VIP_VS_BLANKING_CNTL			0x0544