radeon.h

原名叫avifile

#	define GRAPHIC_KEY_FN_TRUE		0x00000010L
#	define GRAPHIC_KEY_FN_EQ		0x00000020L
#	define GRAPHIC_KEY_FN_NE		0x00000030L
#endif
#	define CMP_MIX_MASK			0x00000100L
#	define CMP_MIX_OR			0x00000000L
#	define CMP_MIX_AND			0x00000100L
#define	OV0_TEST				0x04F8
#	define OV0_SCALER_Y2R_DISABLE		0x00000001L
#	define OV0_SUBPIC_ONLY			0x00000008L
#	define OV0_EXTENSE			0x00000010L
#	define OV0_SWAP_UV			0x00000020L
#define OV0_COL_CONV				0x04FC
#	define OV0_CB_TO_B			0x0000007FL
#	define OV0_CB_TO_G			0x0000FF00L
#	define OV0_CR_TO_G			0x00FF0000L
#	define OV0_CR_TO_R			0x7F000000L
#	define OV0_NEW_COL_CONV			0x80000000L
#define	OV0_LIN_TRANS_A				0x0D20
#define	OV0_LIN_TRANS_B				0x0D24
#define	OV0_LIN_TRANS_C				0x0D28
#define	OV0_LIN_TRANS_D				0x0D2C
#define	OV0_LIN_TRANS_E				0x0D30
#define	OV0_LIN_TRANS_F				0x0D34
#define	OV0_GAMMA_0_F				0x0D40
#define	OV0_GAMMA_10_1F				0x0D44
#define	OV0_GAMMA_20_3F				0x0D48
#define	OV0_GAMMA_40_7F				0x0D4C
/* These registers exist on R200 only */
#define OV0_GAMMA_80_BF				0x0E00
#define OV0_GAMMA_C0_FF				0x0E04
#define OV0_GAMMA_100_13F			0x0E08
#define OV0_GAMMA_140_17F			0x0E0C
#define OV0_GAMMA_180_1BF			0x0E10
#define OV0_GAMMA_1C0_1FF			0x0E14
#define OV0_GAMMA_200_23F			0x0E18
#define OV0_GAMMA_240_27F			0x0E1C
#define OV0_GAMMA_280_2BF			0x0E20
#define OV0_GAMMA_2C0_2FF			0x0E24
#define OV0_GAMMA_300_33F			0x0E28
#define OV0_GAMMA_340_37F			0x0E2C
/* End of R200 specific definitions */
#define	OV0_GAMMA_380_3BF			0x0D50
#define	OV0_GAMMA_3C0_3FF			0x0D54

/*
 IDCT ENGINE:
 It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag
 and IDCT into an IDCT engine to complement the motion compensation engine.
*/
#define IDCT_RUNS				0x1F80
#define IDCT_LEVELS				0x1F84
#define IDCT_AUTH_CONTROL			0x1F88
#define IDCT_AUTH				0x1F8C
#define IDCT_CONTROL				0x1FBC

#define SE_MC_SRC2_CNTL				0x19D4
#	define SECONDARY_SCALE_HACC		0x00001FFFL
#	define SECONDARY_SCALE_VACC		0x0FFF0000L
#	define SECONDARY_SCALE_PICTH_ADJ	0xC0000000L
#define SE_MC_SRC1_CNTL				0x19D8
#	define SCALE_HACC			0x00001FFFL
#	define SCALE_VACC			0x0FFF0000L
#	define IDCT_EN				0x10000000L
#	define SECONDARY_TEX_EN			0x20000000L
#	define SCALE_PICTH_ADJ			0xC0000000L
#define SE_MC_DST_CNTL				0x19DC
#	define DST_Y				0x00003FFFL
#	define DST_X				0x3FFF0000L
#	define DST_PITCH_ADJ			0xC0000000L
#define SE_MC_CNTL_START			0x19E0
#	define SCALE_OFFSET_PTR			0x0000000FL
#	define DST_OFFSET			0x00FFFFF0L
#	define ALPHA_EN				0x01000000L
#	define SECONDARY_OFFSET_PTR		0x1E000000L
#	define MC_DST_HEIGHT_WIDTH		0xE0000000L
#ifndef RAGE128
#define SE_MC_BUF_BASE				0x19E4
#define PP_MC_CONTEXT				0x19E8
#define PP_MISC					0x1C14
#endif
/*
   SUBPICTURE UNIT:
   Decompressing, scaling and alpha blending the compressed bitmap on the fly.
   Provide optimal DVD subpicture qualtity.
*/
#define	SUBPIC_CNTL				0x0540
#define	SUBPIC_DEFCOLCON			0x0544
#define	SUBPIC_Y_X_START			0x054C
#define	SUBPIC_Y_X_END				0x0550
#define	SUBPIC_V_INC				0x0554
#define	SUBPIC_H_INC				0x0558
#define	SUBPIC_BUF0_OFFSET			0x055C
#define	SUBPIC_BUF1_OFFSET			0x0560
#define	SUBPIC_LC0_OFFSET			0x0564
#define	SUBPIC_LC1_OFFSET			0x0568
#define	SUBPIC_PITCH				0x056C
#define	SUBPIC_BTN_HLI_COLCON			0x0570
#define	SUBPIC_BTN_HLI_Y_X_START		0x0574
#define	SUBPIC_BTN_HLI_Y_X_END			0x0578
#define	SUBPIC_PALETTE_INDEX			0x057C
#define	SUBPIC_PALETTE_DATA			0x0580
#define	SUBPIC_H_ACCUM_INIT			0x0584
#define	SUBPIC_V_ACCUM_INIT			0x0588

#define CP_RB_BASE				0x0700
#define CP_RB_CNTL				0x0704
#define CP_RB_RPTR_ADDR				0x070C
#define CP_RB_RPTR				0x0710
#define CP_RB_WPTR				0x0714
#define CP_RB_WPTR_DELAY			0x0718
#define CP_IB_BASE				0x0738
#define CP_IB_BUFSZ				0x073C
#define CP_CSQ_CNTL				0x0740
#define SCRATCH_UMSK				0x0770
#define SCRATCH_ADDR				0x0774
#ifndef RAGE128
#define DMA_GUI_TABLE_ADDR			0x0780
#	define DMA_GUI_COMMAND__BYTE_COUNT_MASK	0x001fffff
#	define DMA_GUI_COMMAND__INTDIS		0x40000000
#	define DMA_GUI_COMMAND__EOL		0x80000000
#define DMA_GUI_SRC_ADDR			0x0784
#define DMA_GUI_DST_ADDR			0x0788
#define DMA_GUI_COMMAND				0x078C
#define DMA_GUI_STATUS				0x0790
#define DMA_GUI_ACT_DSCRPTR			0x0794
#define DMA_VID_TABLE_ADDR			0x07A0
#define DMA_VID_SRC_ADDR			0x07A4
#define DMA_VID_DST_ADDR			0x07A8
#define DMA_VID_COMMAND				0x07AC
#define DMA_VID_STATUS				0x07B0
#define DMA_VID_ACT_DSCRPTR			0x07B4
#endif
#define CP_ME_CNTL				0x07D0
#define CP_ME_RAM_ADDR				0x07D4
#define CP_ME_RAM_RADDR				0x07D8
#define CP_ME_RAM_DATAH				0x07DC
#define CP_ME_RAM_DATAL				0x07E0
#define CP_CSQ_ADDR				0x07F0
#define CP_CSQ_DATA				0x07F4
#define CP_CSQ_STAT				0x07F8

#define	DISP_MISC_CNTL				0x0D00
#	define SOFT_RESET_GRPH_PP		(1 << 0)
#define	DAC_MACRO_CNTL				0x0D04
#define	DISP_PWR_MAN				0x0D08
#define	DISP_TEST_DEBUG_CNTL			0x0D10
#define	DISP_HW_DEBUG				0x0D14
#define	DAC_CRC_SIG1				0x0D18
#define	DAC_CRC_SIG2				0x0D1C

/* first capture unit */

#define	VID_BUFFER_CONTROL			0x0900
#define CAP_INT_CNTL				0x0908
#define CAP_INT_STATUS				0x090C
#define FCP_CNTL				0x0910
#	define FCP_CNTL__PCICLK			0
#	define FCP_CNTL__PCLK			1
#	define FCP_CNTL__PCLKb			2
#	define FCP_CNTL__HREF			3
#	define FCP_CNTL__GND			4
#	define FCP_CNTL__HREFb			5

#define	CAP0_BUF0_OFFSET			0x0920
#define	CAP0_BUF1_OFFSET			0x0924
#define	CAP0_BUF0_EVEN_OFFSET			0x0928
#define	CAP0_BUF1_EVEN_OFFSET			0x092C
#define	CAP0_BUF_PITCH				0x0930
#define	CAP0_V_WINDOW				0x0934
#define	CAP0_H_WINDOW				0x0938
#define	CAP0_VBI0_OFFSET			0x093C
#define	CAP0_VBI1_OFFSET			0x0940
#define	CAP0_VBI_V_WINDOW			0x0944
#define	CAP0_VBI_H_WINDOW			0x0948
#define	CAP0_PORT_MODE_CNTL			0x094C
#define	CAP0_TRIG_CNTL				0x0950
#define	CAP0_DEBUG				0x0954
#define	CAP0_CONFIG				0x0958
#	define CAP0_CONFIG_CONTINUOS		0x00000001
#	define CAP0_CONFIG_START_FIELD_EVEN	0x00000002
#	define CAP0_CONFIG_START_BUF_GET	0x00000004
#	define CAP0_CONFIG_START_BUF_SET	0x00000008
#	define CAP0_CONFIG_BUF_TYPE_ALT		0x00000010
#	define CAP0_CONFIG_BUF_TYPE_FRAME	0x00000020
#	define CAP0_CONFIG_ONESHOT_MODE_FRAME	0x00000040
#	define CAP0_CONFIG_BUF_MODE_DOUBLE	0x00000080
#	define CAP0_CONFIG_BUF_MODE_TRIPLE	0x00000100
#	define CAP0_CONFIG_MIRROR_EN		0x00000200
#	define CAP0_CONFIG_ONESHOT_MIRROR_EN	0x00000400
#	define CAP0_CONFIG_VIDEO_SIGNED_UV	0x00000800
#	define CAP0_CONFIG_ANC_DECODE_EN	0x00001000
#	define CAP0_CONFIG_VBI_EN		0x00002000
#	define CAP0_CONFIG_SOFT_PULL_DOWN_EN	0x00004000
#	define CAP0_CONFIG_VIP_EXTEND_FLAG_EN	0x00008000
#	define CAP0_CONFIG_FAKE_FIELD_EN	0x00010000
#	define CAP0_CONFIG_ODD_ONE_MORE_LINE	0x00020000
#	define CAP0_CONFIG_EVEN_ONE_MORE_LINE	0x00040000
#	define CAP0_CONFIG_HORZ_DIVIDE_2	0x00080000
#	define CAP0_CONFIG_HORZ_DIVIDE_4	0x00100000
#	define CAP0_CONFIG_VERT_DIVIDE_2	0x00200000
#	define CAP0_CONFIG_VERT_DIVIDE_4	0x00400000
#	define CAP0_CONFIG_FORMAT_BROOKTREE	0x00000000
#	define CAP0_CONFIG_FORMAT_CCIR656	0x00800000
#	define CAP0_CONFIG_FORMAT_ZV		0x01000000
#	define CAP0_CONFIG_FORMAT_VIP		0x01800000
#	define CAP0_CONFIG_FORMAT_TRANSPORT	0x02000000
#	define CAP0_CONFIG_HORZ_DECIMATOR	0x04000000
#	define CAP0_CONFIG_VIDEO_IN_YVYU422	0x00000000
#	define CAP0_CONFIG_VIDEO_IN_VYUY422	0x20000000
#	define CAP0_CONFIG_VBI_DIVIDE_2		0x40000000
#	define CAP0_CONFIG_VBI_DIVIDE_4		0x80000000
#define	CAP0_ANC_ODD_OFFSET			0x095C
#define	CAP0_ANC_EVEN_OFFSET			0x0960
#define	CAP0_ANC_H_WINDOW			0x0964
#define	CAP0_VIDEO_SYNC_TEST			0x0968
#define	CAP0_ONESHOT_BUF_OFFSET			0x096C
#define	CAP0_BUF_STATUS				0x0970
#ifdef RAGE128
#define	CAP0_DWNSC_XRATIO			0x0978
#define	CAP0_XSHARPNESS				0x097C
#else
/* #define CAP0_DWNSC_XRATIO			0x0978 */
/* #define CAP0_XSHARPNESS			0x097C */
#endif
#define	CAP0_VBI2_OFFSET			0x0980
#define	CAP0_VBI3_OFFSET			0x0984
#define	CAP0_ANC2_OFFSET			0x0988
#define	CAP0_ANC3_OFFSET			0x098C

/* second capture unit */

#define	CAP1_BUF0_OFFSET			0x0990
#define	CAP1_BUF1_OFFSET			0x0994
#define	CAP1_BUF0_EVEN_OFFSET			0x0998
#define	CAP1_BUF1_EVEN_OFFSET			0x099C

#define	CAP1_BUF_PITCH				0x09A0
#define	CAP1_V_WINDOW				0x09A4
#define	CAP1_H_WINDOW				0x09A8
#define	CAP1_VBI_ODD_OFFSET			0x09AC
#define	CAP1_VBI_EVEN_OFFSET			0x09B0
#define	CAP1_VBI_V_WINDOW			0x09B4
#define	CAP1_VBI_H_WINDOW			0x09B8
#define	CAP1_PORT_MODE_CNTL			0x09BC
#define	CAP1_TRIG_CNTL				0x09C0
#define	CAP1_DEBUG				0x09C4
#define	CAP1_CONFIG				0x09C8
#define	CAP1_ANC_ODD_OFFSET			0x09CC
#define	CAP1_ANC_EVEN_OFFSET			0x09D0
#define	CAP1_ANC_H_WINDOW			0x09D4
#define	CAP1_VIDEO_SYNC_TEST			0x09D8
#define	CAP1_ONESHOT_BUF_OFFSET			0x09DC
#define	CAP1_BUF_STATUS				0x09E0
#define	CAP1_DWNSC_XRATIO			0x09E8
#define	CAP1_XSHARPNESS				0x09EC

#define	DISP_MERGE_CNTL				0x0D60
#define	DISP_OUTPUT_CNTL			0x0D64
#	define DISP_DAC_SOURCE_MASK		0x03
#	define DISP_DAC_SOURCE_CRTC2		0x01
#define	DISP_LIN_TRANS_GRPH_A			0x0D80
#define	DISP_LIN_TRANS_GRPH_B			0x0D84
#define	DISP_LIN_TRANS_GRPH_C			0x0D88
#define	DISP_LIN_TRANS_GRPH_D			0x0D8C
#define	DISP_LIN_TRANS_GRPH_E			0x0D90
#define	DISP_LIN_TRANS_GRPH_F			0x0D94
#define	DISP_LIN_TRANS_VID_A			0x0D98
#define	DISP_LIN_TRANS_VID_B			0x0D9C
#define	DISP_LIN_TRANS_VID_C			0x0DA0
#define	DISP_LIN_TRANS_VID_D			0x0DA4
#define	DISP_LIN_TRANS_VID_E			0x0DA8
#define	DISP_LIN_TRANS_VID_F			0x0DAC
#define	RMX_HORZ_FILTER_0TAP_COEF		0x0DB0
#define	RMX_HORZ_FILTER_1TAP_COEF		0x0DB4
#define	RMX_HORZ_FILTER_2TAP_COEF		0x0DB8
#define	RMX_HORZ_PHASE				0x0DBC
#define	DAC_EMBEDDED_SYNC_CNTL			0x0DC0
#define	DAC_BROAD_PULSE				0x0DC4
#define	DAC_SKEW_CLKS				0x0DC8
#define	DAC_INCR				0x0DCC
#define	DAC_NEG_SYNC_LEVEL			0x0DD0
#define	DAC_POS_SYNC_LEVEL			0x0DD4
#define	DAC_BLANK_LEVEL				0x0DD8
#define	CLOCK_CNTL_INDEX			0x0008
/* CLOCK_CNTL_INDEX bit	constants */
#	define PLL_WR_EN			0x00000080
#	define PLL_DIV_SEL			(3 << 8)
#	define PLL2_DIV_SEL_MASK		~(3 << 8)
#define	CLOCK_CNTL_DATA				0x000C
#define	CP_RB_CNTL				0x0704
#define	CP_RB_BASE				0x0700
#define	CP_RB_RPTR_ADDR				0x070C
#define	CP_RB_RPTR				0x0710
#define	CP_RB_WPTR				0x0714
#define	CP_RB_WPTR_DELAY			0x0718
#define	CP_IB_BASE				0x0738
#define	CP_IB_BUFSZ				0x073C
#define	SCRATCH_REG0				0x15E0
#define	GUI_SCRATCH_REG0			0x15E0
#define	SCRATCH_REG1				0x15E4
#define	GUI_SCRATCH_REG1			0x15E4
#define	SCRATCH_REG2				0x15E8
#define	GUI_SCRATCH_REG2			0x15E8
#define	SCRATCH_REG3				0x15EC
#define	GUI_SCRATCH_REG3			0x15EC
#define	SCRATCH_REG4				0x15F0
#define	GUI_SCRATCH_REG4			0x15F0
#define	SCRATCH_REG5				0x15F4
#define	GUI_SCRATCH_REG5			0x15F4
#define	SCRATCH_UMSK				0x0770
#define	SCRATCH_ADDR				0x0774
#define	DP_BRUSH_FRGD_CLR			0x147C
#define	DP_BRUSH_BKGD_CLR			0x1478
#define	DST_LINE_START				0x1600
#define	DST_LINE_END				0x1604
#define	SRC_OFFSET				0x15AC
#define	SRC_PITCH				0x15B0
#define	SRC_TILE				0x1704
#define	SRC_PITCH_OFFSET			0x1428
#define	SRC_X					0x1414
#define	SRC_Y					0x1418
#define DST_WIDTH_X				0x1588
#define DST_HEIGHT_WIDTH_8			0x158C
#define	SRC_X_Y					0x1590
#define	SRC_Y_X					0x1434
#define	DST_Y_X					0x1438
#define	DST_WIDTH_HEIGHT			0x1598
#define	DST_HEIGHT_WIDTH			0x143c
#ifdef RAGE128
#define GUI_STAT				0x1740
#	define GUI_FIFOCNT_MASK			0x0fff
#	define PM4_BUSY				(1 << 16)
#	define MICRO_BUSY			(1 << 17)
#	define FPU_BUSY				(1 << 18)
#	define VC_BUSY				(1 << 19)
#	define IDCT_BUSY			(1 << 20)
#	define ENG_EV_BUSY			(1 << 21)
#	define SETUP_BUSY			(1 << 22)
#	define EDGE_WALK_BUSY			(1 << 23)
#	define ADDRESSING_BUSY			(1 << 24)
#	define ENG_3D_BUSY			(1 << 25)
#	define ENG_2D_SM_BUSY			(1 << 26)
#	define ENG_2D_BUSY			(1 << 27)
#	define GUI_WB_BUSY			(1 << 28)
#	define CACHE_BUSY			(1 << 29)
#	define GUI_ACTIVE			(1 << 31)
#endif
#define	SRC_CLUT_ADDRESS			0x1780
#define	SRC_CLUT_DATA				0x1784
#define	SRC_CLUT_DATA_RD			0x1788
#define	HOST_DATA0				0x17C0
#define	HOST_DATA1				0x17C4
#define	HOST_DATA2				0x17C8
#define	HOST_DATA3				0x17CC
#define	HOST_DATA4				0x17D0
#define	HOST_DATA5				0x17D4
#define	HOST_DATA6				0x17D8
#define	HOST_DATA7				0x17DC
#define	HOST_DATA_LAST				0x17E0
#define	DP_SRC_ENDIAN				0x15D4
#define	DP_SRC_FRGD_CLR				0x15D8
#define	DP_SRC_BKGD_CLR				0x15DC
#define	DP_WRITE_MASK				0x16cc
#define	SC_LEFT					0x1640
#define	SC_RIGHT				0x1644
#define	SC_TOP					0x1648
#define	SC_BOTTOM				0x164C
#define	SRC_SC_RIGHT				0x1654
#define	SRC_SC_BOTTOM				0x165C
#define	DP_CNTL					0x16C0
/* DP_CNTL bit constants */
#	define DST_X_RIGHT_TO_LEFT		0x00000000
#	define DST_X_LEFT_TO_RIGHT		0x00000001
#	define DST_Y_BOTTOM_TO_TOP		0x00000000