cable.mdl

matlab中用于解决高等动力学hamilton系统的相关程序

Model {
  Name			  "cable"
  Version		  5.0
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ExecutionOrder	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Tue Dec 30 02:11:55 2003"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "Ahamd Colahi"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Tue Dec 30 03:38:07 2003"
  ModelVersionFormat	  "1.%<AutoIncrement:6>"
  ConfigurationManager	  "None"
  SimParamPage		  "Solver"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  RTWExpressionDepthLimit 5
  SimulationMode	  "normal"
  Solver		  "ode45"
  SolverMode		  "Auto"
  StartTime		  "0.0"
  StopTime		  "10.0"
  MaxOrder		  5
  MaxStep		  "auto"
  MinStep		  "auto"
  MaxNumMinSteps	  "-1"
  InitialStep		  "auto"
  FixedStep		  "auto"
  RelTol		  "1e-3"
  AbsTol		  "auto"
  OutputOption		  "RefineOutputTimes"
  OutputTimes		  "[]"
  Refine		  "1"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveTime		  on
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  on
  OutputSaveName	  "yout"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  SaveFormat		  "Array"
  Decimation		  "1"
  LimitDataPoints	  on
  MaxDataPoints		  "1000"
  SignalLoggingName	  "sigsOut"
  ConsistencyChecking	  "none"
  ArrayBoundsChecking	  "none"
  AlgebraicLoopMsg	  "warning"
  BlockPriorityViolationMsg "warning"
  MinStepSizeMsg	  "warning"
  InheritedTsInSrcMsg	  "warning"
  DiscreteInheritContinuousMsg "warning"
  MultiTaskRateTransMsg	  "error"
  SingleTaskRateTransMsg  "none"
  CheckForMatrixSingularity "none"
  IntegerOverflowMsg	  "warning"
  Int32ToFloatConvMsg	  "warning"
  ParameterDowncastMsg	  "error"
  ParameterOverflowMsg	  "error"
  ParameterPrecisionLossMsg "warning"
  UnderSpecifiedDataTypeMsg "none"
  UnnecessaryDatatypeConvMsg "none"
  VectorMatrixConversionMsg "none"
  InvalidFcnCallConnMsg	  "error"
  SignalLabelMismatchMsg  "none"
  UnconnectedInputMsg	  "warning"
  UnconnectedOutputMsg	  "warning"
  UnconnectedLineMsg	  "warning"
  SfunCompatibilityCheckMsg "none"
  RTWInlineParameters	  off
  BlockReductionOpt	  on
  BooleanDataType	  on
  ConditionallyExecuteInputs on
  ParameterPooling	  on
  OptimizeBlockIOStorage  on
  ZeroCross		  on
  AssertionControl	  "UseLocalSettings"
  ProdHWDeviceType	  "Microprocessor"
  ProdHWWordLengths	  "8,16,32,32"
  RTWSystemTargetFile	  "grt.tlc"
  RTWTemplateMakefile	  "grt_default_tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  RTWRetainRTWFile	  off
  TLCProfiler		  off
  TLCDebug		  off
  TLCCoverage		  off
  TLCAssertion		  off
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Constant
      Value		      "1"
      VectorParams1D	      on
      ShowAdditionalParam     off
      OutDataTypeMode	      "Inherit from 'Constant value'"
      OutDataType	      "sfix(16)"
      ConRadixGroup	      "Use specified scaling"
      OutScaling	      "2^0"
    }
    Block {
      BlockType		      Fcn
      Expr		      "sin(u[1])"
    }
    Block {
      BlockType		      Inport
      Port		      "1"
      PortDimensions	      "-1"
      SampleTime	      "-1"
      ShowAdditionalParam     off
      LatchInput	      off
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Integrator
      ExternalReset	      "none"
      InitialConditionSource  "internal"
      InitialCondition	      "0"
      LimitOutput	      off
      UpperSaturationLimit    "inf"
      LowerSaturationLimit    "-inf"
      ShowSaturationPort      off
      ShowStatePort	      off
      AbsoluteTolerance	      "auto"
      ZeroCross		      on
    }
    Block {
      BlockType		      Mux
      Inputs		      "4"
      DisplayOption	      "none"
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      PortCounts	      "[]"
      SFunctionModules	      "''"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      RTWSystemCode	      "Auto"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "cable"
    Location		    [2, 82, 1014, 692]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      SubSystem
      Name		      "DEE"
      Ports		      [9, 2]
      Position		      [160, 19, 290, 551]
      OpenFcn		      "diffeqed"
      TreatAsAtomicUnit	      off
      MaskType		      "Differential Equation Editor (DEE)"
      MaskDisplay	      "disp('Differential Equation\\n Editor')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"DEE"
	Location		[100, 100, 600, 400]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "SysInport1"
	  Position		  [20, 52, 45, 78]
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport2"
	  Position		  [20, 102, 45, 128]
	  Port			  "2"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport3"
	  Position		  [20, 152, 45, 178]
	  Port			  "3"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport4"
	  Position		  [20, 202, 45, 228]
	  Port			  "4"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport5"
	  Position		  [20, 252, 45, 278]
	  Port			  "5"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport6"
	  Position		  [20, 302, 45, 328]
	  Port			  "6"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport7"
	  Position		  [20, 352, 45, 378]
	  Port			  "7"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport8"
	  Position		  [20, 402, 45, 428]
	  Port			  "8"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SysInport9"
	  Position		  [20, 452, 45, 478]
	  Port			  "9"
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Integ1"
	  Ports			  [1, 1]
	  Position		  [400, 50, 430, 70]
	  InitialCondition	  "-10"
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Integ2"
	  Ports			  [1, 1]
	  Position		  [400, 100, 430, 120]
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Integ3"
	  Ports			  [1, 1]
	  Position		  [400, 150, 430, 170]
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Integ4"
	  Ports			  [1, 1]
	  Position		  [400, 200, 430, 220]
	}
	Block {
	  BlockType		  Mux
	  Name			  "SysMux"