ezkitsettings.c

ADSP-BF537Display部分的代码

/*=============================================================================
=
= Name:     QVGA Display and Timer Verification and Example Code
=
===============================================================================
=
= (C) Copyright 2006 - Analog Devices, Inc.  All rights reserved.
=
= File Name :   ezkitsettings.c
=
= Date      :   12/21/06
=
= Target    :   ADSP-BF537
=
= Version   :   1.0
=
= Purpose   :   Test the display with a bitmap
=
=
=
==============================================================================*/

#include <services/services.h>
#include <drivers/adi_dev.h>
#include "ezkitsettings.h"
#include "cdefbf537.h"

/*********************************************************************

	Function:		InitPower

	Description:	Initializes the Power Management module and sets 
				    the power settings for CCLK 600 MHz and SCLK 133
				    MHz

*********************************************************************/
ADI_PWR_RESULT InitPower(void)
{
	ADI_PWR_RESULT 	PWRResult;
	
	ADI_PWR_COMMAND_PAIR ezkit_power[] = {	
		{ ADI_PWR_CMD_SET_EZKIT, (void*)ADI_PWR_EZKIT_BF537_600MHZ },
		{ ADI_PWR_CMD_END, (void*)0}											// No more commands
	};	

	PWRResult = adi_pwr_Init(ezkit_power);
	if (PWRResult != ADI_PWR_RESULT_SUCCESS) {
		return PWRResult;
	}

	PWRResult = adi_pwr_SetFreq(400000000, 133000000, ADI_PWR_DF_OFF);
	return PWRResult;	
}

////////////////////////////////////////////////////////////////////////////
// variables required to configure the timing specifications for the 
// Micron MT48LC32M8A2-75 memory modules
//
static ADI_EBIU_TIMING_VALUE sdram_refresh = { 											// SDRAM Refresh rate: 
												8192, 									// 8192 cycles
												{ 64, ADI_EBIU_TIMING_UNIT_MILLISEC	} 	// 64 milliseconds
};

static ADI_EBIU_SDRAM_BANK_VALUE bank_size =  {0, ADI_EBIU_SDRAM_BANK_64MB};			// 64MB 

// cast to first union member is used to avoid warning message from compiler
static ADI_EBIU_SDRAM_BANK_VALUE bank_caw = {0, (ADI_EBIU_SDRAM_BANK_SIZE)ADI_EBIU_SDRAM_BANK_COL_10BIT}; // 10 bit column addess width

static ADI_EBIU_TIME ebiu_44_nanosecs = {44, ADI_EBIU_TIMING_UNIT_NANOSEC};				// 44 nanoseconds
static ADI_EBIU_TIME ebiu_20_nanosecs = {20, ADI_EBIU_TIMING_UNIT_NANOSEC};				// 20 nanoseconds
static ADI_EBIU_TIMING_VALUE twr_min = { 												// Minimum TWR value
												1, 										// 1 cycle
												{7500, ADI_EBIU_TIMING_UNIT_PICOSEC} 	// 7.5 nanoseconds
};

#define DO_NOT_CHANGE_MMR_SETTINGS 0

/*********************************************************************

	Function:		InitSDRAM

	Description:	Initializes the EBIU module with the required SDRAM 
				    settings.

*********************************************************************/
ADI_EBIU_RESULT InitSDRAM(void)
{
	ADI_EBIU_RESULT EBIUResult;
	
	// The following command table describes the configuration for
	// Micron MT48LC32M16A2-75 (8MB x 16 x 4 banks) memory modules to
	// give a total of 64MB.
	//
	ADI_EBIU_COMMAND_PAIR ezkit_sdram[] = {	
		{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE,		(void*)&bank_size     		},
		{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_caw    		}, 
		{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD,	(void*)53	          		},
		{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN,		(void*)&ebiu_44_nanosecs   	},
		{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN,		(void*)&ebiu_20_nanosecs   	},
		{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN,		(void*)&ebiu_20_nanosecs   	},
		{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN,		(void*)&twr_min 	        },
		{ ADI_EBIU_CMD_SET_SDRAM_REFRESH,		(void*)&sdram_refresh 		},
		// The next command disables Fast back to back read/write sequences
		// which is safe for all systems
		{ ADI_EBIU_CMD_SET_SDRAM_FBBRW, 		(void*)0					},
		{ ADI_EBIU_CMD_END, 0}
	};
	
	EBIUResult = adi_ebiu_Init( ezkit_sdram, DO_NOT_CHANGE_MMR_SETTINGS );
	return EBIUResult;
}

void ConfigureAsync (void)
{
	*pEBIU_AMGCTL	= AMCKEN | AMBEN_B0_B1 ;//| CDPRIO;	
	//*pEBIU_AMBCTL0	= 0xffc2ffc2;
	//*pEBIU_AMBCTL1	= 0x13d0ffc2;
}