cyrf6936.c

cypress6936无线收发器avr驱动

#include ".\cyrf6936.h"

struct_cyrf6936_common_status cyrf6936_current_status;
struct_cyrf6936_common_config cyrf6936_current_config;

struct_rb_byte_id cyrf6936_rx_rb_id;
struct_rb_byte_id cyrf6936_tx_rb_id;
U8 cyrf6936_rx_buffer[CYRF6936_RX_BUFFER_LENGTH];
U8 cyrf6936_tx_buffer[CYRF6936_TX_BUFFER_LENGTH];
status cyrf6936_transmit_flag = ready;
status cyrf6936_receive_flag = ready;

status cyrf_spi_transfer_flag = ready;

S32 cyrf_spi_read(S8 adr, S8 * p_rst, int length)
{
	U8 temp_u8bits = 0;
	U32 temp_s32bits = 0;

	if(cyrf_spi_transfer_flag != ready) {
		return 0;
	}

	cyrf_spi_transfer_flag = busy;
	change_spi_nss(0);

	/* wait for last spi transfer complete. */
	while(spi_transmit_flag == busy);

	/* clear spi receive buffer. */
	while(rb_byte_read(&spi_rx_rb_id, 1, &temp_u8bits));

	/* create the byte1, address */
	temp_u8bits = (adr&CYRF6936_SPI_ADR_MASK)|CYRF6936_SPI_READ_SINGLE_CMD;
	rb_byte_write(&spi_tx_rb_id, 1, &temp_u8bits);

	/* send data. */
	rb_byte_write(&spi_tx_rb_id, length, p_rst);
	spi_transmit_startup();

	/* wait for last spi transfer complete. */
	while(spi_transmit_flag == busy);

	/* receive data. */
	rb_byte_read(&spi_rx_rb_id, 1, &temp_u8bits);
	temp_s32bits = rb_byte_read(&spi_rx_rb_id, length, p_rst);

	change_spi_nss(1);
	cyrf_spi_transfer_flag = ready;

	return temp_s32bits;
}

S32 cyrf_spi_write(S8 adr, S8 * p_src, int length)
{
	U8 temp_u8bits = 0;
	S32 temp_s32bits = 0;

	if(cyrf_spi_transfer_flag != ready) {
		return 0;
	}

	cyrf_spi_transfer_flag = busy;
	change_spi_nss(0);

	/* wait for last spi transfer complete. */
	while(spi_transmit_flag == busy);

	/* clear spi receive buffer. */
	while(rb_byte_read(&spi_rx_rb_id, 1, &temp_u8bits));

	/* create the byte1, address */
	temp_u8bits = (adr&CYRF6936_SPI_ADR_MASK)|CYRF6936_SPI_WRITE_SINGLE_CMD;
	rb_byte_write(&spi_tx_rb_id, 1, &temp_u8bits);

	/* send data. */
	temp_s32bits = rb_byte_write(&spi_tx_rb_id, length, p_src);
	spi_transmit_startup();

	/* wait for last spi transfer complete. */
	while(spi_transmit_flag == busy);

	/* clear spi receive buffer. */
	while(rb_byte_read(&spi_rx_rb_id, 1, &temp_u8bits));

	change_spi_nss(1);
	cyrf_spi_transfer_flag = ready;

	return temp_s32bits;

}

status cyrf6936_init()
{
	int i;
	union_cyrf6936_common_trx common_trx;
	U8 data1,data2;
	U8 temp_adr = CYRF6936_REG_CHANNEL_ADR;
	int temp_int = 0;

	/* clear current configure data. */
	for(i = 0; i < sizeof(cyrf6936_current_config); i++) {
		((U8 *)&cyrf6936_current_config)[i] = 0;
	}

	/* test */
	while(1) {
		temp_int = cyrf_spi_read(temp_adr, &data1, 1);
		data2 = 0;
		/* temp_int = cyrf_spi_write(temp_adr, &data2, 1); */
		temp_int = cyrf_spi_read(temp_adr, &data1, 1);
	}

	/* reset cyrf6936. */
	cyrf6936_current_config.mode_override_adr.byte = 0;
	cyrf6936_current_config.mode_override_adr.bits.RST = 1;
	while(cyrf_spi_write(CYRF6936_REG_MODE_OVERRIDE_ADR, &(cyrf6936_current_config.mode_override_adr.byte), 1));
	cyrf6936_current_config.mode_override_adr.byte = 0;

	/* enable cyrf6936 synthesizer. */
	cyrf6936_current_config.mode_override_adr.byte = 0;
	cyrf6936_current_config.mode_override_adr.bits.FRC_SEN = 1;
	while(cyrf_spi_write(CYRF6936_REG_MODE_OVERRIDE_ADR, &(cyrf6936_current_config.mode_override_adr.byte), 1));
	cyrf6936_current_config.mode_override_adr.byte = 0;

	/* channel=2496MHz, type=fast. */
	cyrf6936_current_config.channel_adr.byte = 0;
	cyrf6936_current_config.channel_adr.bits.CHANNEL = 96;
	while(cyrf_spi_write(CYRF6936_REG_CHANNEL_ADR, &(cyrf6936_current_config.channel_adr.byte), 1));

	/* data mode = GFSK, PA = -20dBm.  */
	cyrf6936_current_config.tx_cfg_adr.byte = 0;
	cyrf6936_current_config.tx_cfg_adr.bits.DATA_MODE = CYRF6936_DATA_MODE_GFSK;
	cyrf6936_current_config.tx_cfg_adr.bits.PA_SETTING = CYRF6936_PA_LEVEL_n20dBm;
	while(cyrf_spi_write(CYRF6936_REG_TX_CFG_ADR, &(cyrf6936_current_config.tx_cfg_adr.byte), 1));

	/* disable AGC and attenuator and fast turn and receive valid flag, enable LNA and receive overwrite. */
	cyrf6936_current_config.rx_cfg_adr.byte = 0;
	cyrf6936_current_config.rx_cfg_adr.bits.AGC_EN = 0;
	cyrf6936_current_config.rx_cfg_adr.bits.LNA = 1;
	cyrf6936_current_config.rx_cfg_adr.bits.ATT = 0;
	cyrf6936_current_config.rx_cfg_adr.bits.FAST_TURN_EN = 0;
	cyrf6936_current_config.rx_cfg_adr.bits.RXOW_EN = 1;
	cyrf6936_current_config.rx_cfg_adr.bits.VLD_EN = 0;
	while(cyrf_spi_write(CYRF6936_REG_RX_CFG_ADR, &(cyrf6936_current_config.rx_cfg_adr.byte), 1));

	/* disable the power manage. */
	cyrf6936_current_config.pwr_ctrl_adr.byte = 0;
	cyrf6936_current_config.pwr_ctrl_adr.bits.PMU_EN = 0;
	cyrf6936_current_config.pwr_ctrl_adr.bits.PMU_SEN = 1;
	while(cyrf_spi_write(CYRF6936_REG_PWR_CTRL_ADR, &(cyrf6936_current_config.pwr_ctrl_adr.byte), 1));

	/* set xtal out frequency = 0.75MHz, disable crystal stable interrupt. */
	cyrf6936_current_config.xtal_ctrl_adr.bits.FREQ = 4;
	while(cyrf_spi_write(CYRF6936_REG_XTAL_CTRL_ADR, &(cyrf6936_current_config.xtal_ctrl_adr.byte), 1));

	/* enable the irq pin and set spi to 4-wire mode. */
	cyrf6936_current_config.io_cfg_adr.byte = 0;
	while(cyrf_spi_write(CYRF6936_REG_PWR_CTRL_ADR, &(cyrf6936_current_config.pwr_ctrl_adr.byte), 1));

	/* enable auto-ack. */
	cyrf6936_current_config.xact_cfg_adr.byte = 0;
	cyrf6936_current_config.xact_cfg_adr.bits.ACK_EN = 1;
	while(cyrf_spi_write(CYRF6936_REG_XACT_CFG_ADR, &(cyrf6936_current_config.xact_cfg_adr.byte), 1));

	/* enable SOP and tx length, SOP threshold = 4 for SOP32 */
	cyrf6936_current_config.framing_cfg_adr.byte = 0;
	cyrf6936_current_config.framing_cfg_adr.bits.SOP_EN = 1;
	cyrf6936_current_config.framing_cfg_adr.bits.LEN_EN = 1;
	cyrf6936_current_config.framing_cfg_adr.bits.SOP_TH = 4;
	while(cyrf_spi_write(CYRF6936_REG_FRAMING_CFG_ADR, &(cyrf6936_current_config.framing_cfg_adr.byte), 1));

	/* force enable clock. */
	cyrf6936_current_config.clk_en_adr.byte = 0;
	cyrf6936_current_config.clk_en_adr.bits.RXF = 1;
	while(cyrf_spi_write(CYRF6936_REG_CLK_EN_ADR, &(cyrf6936_current_config.clk_en_adr.byte), 1));
	cyrf6936_current_config.clk_en_adr.bits.RXF = 0;

	/* must write 0x3c for auto-cal time. */
	cyrf6936_current_config.auto_cal_time_adr = 0x3c;
	while(cyrf_spi_write(CYRF6936_REG_AUTO_CAL_TIME_ADR, &(cyrf6936_current_config.auto_cal_time_adr), 1));

	/* must write 0x14 for auto-offset time. */
	cyrf6936_current_config.auto_cal_offset_adr = 0x14;
	while(cyrf_spi_write(CYRF6936_REG_AUTO_CAL_OFFSET_ADR, &(cyrf6936_current_config.auto_cal_offset_adr), 1));

	/* create buffer. */
	rb_byte_create(&cyrf6936_rx_rb_id, cyrf6936_rx_buffer, CYRF6936_RX_BUFFER_LENGTH);
	rb_byte_create(&cyrf6936_tx_rb_id, cyrf6936_tx_buffer, CYRF6936_TX_BUFFER_LENGTH);

	/* setup tx and rx */
	common_trx.tx_ctrl_adr.byte = 0;
	/* common_trx.tx_ctrl_adr.bits.TXC_IRQEN = 1;
	common_trx.tx_ctrl_adr.bits.TXB0_IRQEN = 1;
	common_trx.tx_ctrl_adr.bits.TX_CLR = 1; */
	common_trx.tx_ctrl_adr.byte = 0x4a;
	cyrf_spi_write(CYRF6936_REG_TX_CTRL_ADR, &(common_trx.tx_ctrl_adr.byte), 1);
	common_trx.rx_ctrl_adr.byte = 0;
	/* common_trx.rx_ctrl_adr.bits.RXC_IRQEN = 1;
	common_trx.rx_ctrl_adr.bits.RXB16IRQEN = 1; */
	common_trx.tx_ctrl_adr.byte = 0x22;
	cyrf_spi_write(CYRF6936_REG_RX_CTRL_ADR, &(common_trx.rx_ctrl_adr.byte), 1);

	return ok;
}


status int0_handle()
{
	int i;
	U8 temp_u8bits;
	S32 temp_s32bits;
	union_cyrf6936_reg_rx_irq_status_adr rx_status;
	union_cyrf6936_reg_rx_ctrl_adr rx_ctrl_data;
	union_cyrf6936_reg_tx_irq_status_adr tx_status;

	cyrf_spi_read(CYRF6936_REG_RX_IRQ_STATUS_ADR, &(rx_status.byte), 1);
	cyrf_spi_read(CYRF6936_REG_TX_IRQ_STATUS_ADR, &(tx_status.byte), 1);

	if(rx_status.bits.RXC_IRQ) {
		/* restart rx. */
		cyrf_spi_read(CYRF6936_REG_RX_CTRL_ADR, &(rx_ctrl_data.byte), 1);
		if(rx_ctrl_data.bits.RX_GO != 1) {
			rx_ctrl_data.bits.RX_GO = 1;
			cyrf_spi_write(CYRF6936_REG_RX_CTRL_ADR, &(rx_ctrl_data.byte), 1);
		}
	}

	if(rx_status.bits.RXB16_IRQ) {
		/* load data into the tx fifo */
		for(i = 0; i < CYRF6936_DEV_RX_FIFO_LENGTH; i+=1) {
			cyrf_spi_read(CYRF6936_REGF_RX_BUFFER_ADR, &temp_u8bits, 1);
			rb_byte_write(&cyrf6936_rx_rb_id, 1, &temp_u8bits);
		}
	}

	if(tx_status.bits.TXC_IRQ) {
		/* transmission complete. */
		cyrf6936_transmit_flag = ready;
	}

	if(tx_status.bits.TXB0_IRQ) {
		/* load data into the tx fifo */
		for(i = 0; i < CYRF6936_DEV_TX_FIFO_LENGTH; i+=1) {
			temp_s32bits = rb_byte_read(&cyrf6936_tx_rb_id, 1, &temp_u8bits);
			if(temp_s32bits != 1) {
				break;
			}
			cyrf_spi_write(CYRF6936_REGF_TX_BUFFER_ADR, &temp_u8bits, 1);
		}
	}

	return ok;
}

status cyrf6936_transmit_startup()
{
	U8 temp_u8bits;
	S32 temp_s32bits;
	union_cyrf6936_reg_tx_ctrl_adr temp_reg;
	int i;
	U8 tx_count = 0;

	if(cyrf6936_transmit_flag == busy) {
		return ok;
	} else {
		cyrf6936_transmit_flag = busy;

		/* clear the tx fifo. */
		cyrf_spi_read(CYRF6936_REG_TX_CTRL_ADR, &(temp_reg.byte), 1);
		temp_reg.bits.TX_CLR = 1;
		cyrf_spi_write(CYRF6936_REG_TX_CTRL_ADR, &(temp_reg.byte), 1);

		/* load data into the tx fifo */
		for(i = 0, tx_count = 0; i < CYRF6936_DEV_TX_FIFO_LENGTH; i+=1) {
			temp_s32bits = rb_byte_read(&cyrf6936_tx_rb_id, 1, &temp_u8bits);
			if(temp_s32bits != 1) {
				break;
			}
			cyrf_spi_write(CYRF6936_REGF_TX_BUFFER_ADR, &temp_u8bits, 1);
			tx_count +=1;
		}

		/* set the transmit length. */
		if(tx_count <= 0) {
			cyrf6936_transmit_flag = ready;		/* no data for transmit. */
			return ok;
		}
		cyrf_spi_write(CYRF6936_REG_TX_LENGTH_ADR, &tx_count, 1);

		/* enable transmit. */
		cyrf_spi_read(CYRF6936_REG_TX_CTRL_ADR, &(temp_reg.byte), 1);
		temp_reg.bits.TX_GO = 1;
		cyrf_spi_write(CYRF6936_REG_TX_CTRL_ADR, &(temp_reg.byte), 1);
	}
	return ok;
}