cyrf6936.h

cypress6936无线收发器avr驱动

#ifndef ____CYRF6936____
#define ____CYRF6936____

/* include */
#include "..\common.h"
#include "..\atmega88\atmega88_p.h"
#include "..\phoenix\rb\rb.h"

/* define */
#define CYRF6936_REG_CHANNEL_ADR			(0x00)
#define CYRF6936_REG_TX_LENGTH_ADR			(0x01)
#define CYRF6936_REG_TX_CTRL_ADR			(0x02)
#define CYRF6936_REG_TX_CFG_ADR				(0x03)
#define CYRF6936_REG_TX_IRQ_STATUS_ADR		(0x04)
#define CYRF6936_REG_RX_CTRL_ADR			(0x05)
#define CYRF6936_REG_RX_CFG_ADR				(0x06)
#define CYRF6936_REG_RX_IRQ_STATUS_ADR		(0x07)
#define CYRF6936_REG_RX_STATUS_ADR			(0x08)
#define CYRF6936_REG_RX_COUNT_ADR			(0x09)
#define CYRF6936_REG_RX_LENGTH_ADR			(0x0a)
#define CYRF6936_REG_PWR_CTRL_ADR			(0x0b)
#define CYRF6936_REG_XTAL_CTRL_ADR			(0x0c)
#define CYRF6936_REG_IO_CTRL_ADR			(0x0d)
#define CYRF6936_REG_GPIO_CTRL_ADR			(0x0e)
#define CYRF6936_REG_XACT_CFG_ADR			(0x0f)
#define CYRF6936_REG_FRAMING_CFG_ADR		(0x10)
#define CYRF6936_REG_DATA32_THOLD_ADR		(0x11)
#define CYRF6936_REG_DATA64_THOLD_ADR		(0x12)
#define CYRF6936_REG_RSSI_ADR				(0x13)
#define CYRF6936_REG_EOP_CTRL_ADR			(0x14)
#define CYRF6936_REG_CRC_SEED_LSB_ADR		(0x15)
#define CYRF6936_REG_CRC_SEED_MSB_ADR		(0x16)
#define CYRF6936_REG_TX_CRC_LSB_ADR			(0x17)
#define CYRF6936_REG_TX_CRC_MSB_ADR			(0x18)
#define CYRF6936_REG_RX_CRC_LSB_ADR			(0x19)
#define CYRF6936_REG_RX_CRC_MSB_ADR			(0x1a)
#define CYRF6936_REG_TX_OFFSET_LSB_ADR		(0x1b)
#define CYRF6936_REG_TX_OFFSET_MSB_ADR		(0x1c)
#define CYRF6936_REG_MODE_OVERRIDE_ADR		(0x1d)
#define CYRF6936_REG_RX_OVERRIDE_ADR		(0x1e)
#define CYRF6936_REG_TX_OVERRIDE_ADR		(0x1f)

#define CYRF6936_REG_CLK_OVERRIDE_ADR		(0x27)
#define CYRF6936_REG_CLK_EN_ADR				(0x28)
#define CYRF6936_REG_RX_ABORT_ADR			(0x29)
#define CYRF6936_REG_AUTO_CAL_TIME_ADR		(0x32)
#define CYRF6936_REG_AUTO_CAL_OFFSET_ADR	(0x35)
#define CYRF6936_REG_ANALOG_CTRL_ADR		(0x39)

#define CYRF6936_REGF_TX_BUFFER_ADR			(0x20)
#define CYRF6936_REGF_RX_BUFFER_ADR			(0x21)
#define CYRF6936_REGF_SOP_CODE_ADR			(0x22)
#define CYRF6936_REGF_DATA_CODE_ADR			(0x23)
#define CYRF6936_REGF_PREAMBLE_ADR			(0x24)
#define CYRF6936_REGF_MFG_ID_ADR			(0x25)

#define CYRF6936_SPI_READ_SINGLE_CMD		(0x00)
#define CYRF6936_SPI_READ_INC_CMD			(0x40)
#define CYRF6936_SPI_WRITE_SINGLE_CMD		(0x80)
#define CYRF6936_SPI_WRITE_INC_CMD			(0xc0)
#define CYRF6936_SPI_ADR_MASK				(0x3f)

#define CYRF6936_PA_LEVEL_n30dBm			(0)
#define CYRF6936_PA_LEVEL_n25dBm			(1)
#define CYRF6936_PA_LEVEL_n20dBm			(2)
#define CYRF6936_PA_LEVEL_n15dBm			(3)
#define CYRF6936_PA_LEVEL_n10dBm			(4)
#define CYRF6936_PA_LEVEL_n5dBm				(5)
#define CYRF6936_PA_LEVEL_0dBm				(6)
#define CYRF6936_PA_LEVEL_p4dBm				(7)
#define CYRF6936_DATA_MODE_GFSK				(0)
#define CYRF6936_DATA_MODE_8DR				(1)
#define CYRF6936_DATA_MODE_DDR				(2)
#define CYRF6936_DATA_MODE_SDR				(3)
#define CYRF6936_DATA_CODE_32_CHIP			(0)
#define CYRF6936_DATA_CODE_64_CHIP			(1)

#define CYRF6936_DEV_TX_FIFO_LENGTH			(16)
#define CYRF6936_DEV_RX_FIFO_LENGTH			(16)
#define CYRF6936_TX_BUFFER_LENGTH			(64)
#define CYRF6936_RX_BUFFER_LENGTH			(64)
/* typedef */
typedef struct tag_struct_cyrf6936_reg_channel_adr {
	U8 CHANNEL:7;	/* bit0..6 */
	U8 reserved:1;	/* bit7, reserved. 0 */
}struct_cyrf6936_reg_channel_adr;
typedef union tag_union_cyrf6936_reg_channel_adr {
	U8 byte;
	struct_cyrf6936_reg_channel_adr bits;
}union_cyrf6936_reg_channel_adr;									/* 0x00, channel_adr */
typedef U8 union_cyrf6936_reg_tx_length_adr;			/* 0x01, tx_length_adr */
typedef struct tag_struct_cyrf6936_reg_tx_ctrl_adr {
	U8 TXE_IRQEN:1;		/* bit0 */
	U8 TXC_IRQEN:1;		/* bit1 */
	U8 TXBERR_IRQEN:1;	/* bit2 */
	U8 TXB0_IRQEN:1;	/* bit3 */
	U8 TXB8_IRQEN:1;	/* bit4 */
	U8 TXB15_IRQEN:1;	/* bit5 */
	U8 TX_CLR:1;		/* bit6 */
	U8 TX_GO:1;			/* bit7 */
}struct_cyrf6936_reg_tx_ctrl_adr;
typedef union tag_union_cyrf6936_reg_tx_ctrl_adr {
	U8 byte;
	struct_cyrf6936_reg_tx_ctrl_adr bits;
}union_cyrf6936_reg_tx_ctrl_adr;									/* 0x02, tx_ctrl_adr */
typedef struct tag_struct_cyrf6936_reg_tx_cfg_adr {
	U8 PA_SETTING:3;		/* bit0..2 */
	U8 DATA_MODE:2;			/* bit3..4 */
	U8 DATA_CODE_LENGTH:1;	/* bit5 */
	U8 reserved:2;			/* bit6..7 */
}struct_cyrf6936_reg_tx_cfg_adr;
typedef union tag_union_cyrf6936_reg_tx_cfg_adr {
	U8 byte;
	struct_cyrf6936_reg_tx_cfg_adr bits;
}union_cyrf6936_reg_tx_cfg_adr;										/* 0x03, tx_cfg_adr */
typedef struct tag_struct_cyrf6936_reg_tx_irq_status_adr {
	U8 TXE_IRQ:1;		/* bit0 */
	U8 TXC_IRQ:1;		/* bit1 */
	U8 TXBERR_IRQ:1;	/* bit2 */
	U8 TXB0_IRQ:1;		/* bit3 */
	U8 TXB8_IRQ:1;		/* bit4 */
	U8 TXB15_IRQ:1;		/* bit5 */
	U8 LV_IRQ:1;		/* bit6 */
	U8 OS_IRQ:1;		/* bit7 */
}struct_cyrf6936_reg_tx_irq_status_adr;
typedef union tag_union_cyrf6936_reg_tx_irq_status_adr {
	U8 byte;
	struct_cyrf6936_reg_tx_irq_status_adr bits;
}union_cyrf6936_reg_tx_irq_status_adr;								/* 0x04, tx_irq_status_adr */
typedef struct tag_struct_cyrf6936_reg_rx_ctrl_adr {
	U8 RXE_IRQEN:1;		/* bit0 */
	U8 RXC_IRQEN:1;		/* bit1 */
	U8 RXBERR_IRQEN:1;	/* bit2 */
	U8 RXB1_IRQEN:1;	/* bit3 */
	U8 RXB8_IRQEN:1;	/* bit4 */
	U8 RXB16IRQEN:1;	/* bit5 */
	U8 RSVD:1;			/* bit6 */
	U8 RX_GO:1;			/* bit7 */
}struct_cyrf6936_reg_rx_ctrl_adr;
typedef union tag_union_cyrf6936_reg_rx_ctrl_adr {
	U8 byte;
	struct_cyrf6936_reg_rx_ctrl_adr bits;
}union_cyrf6936_reg_rx_ctrl_adr;									/* 0x05, rx_ctrl_adr */
typedef struct tag_struct_cyrf6936_reg_rx_cfg_adr {
	U8 VLD_EN:1;		/* bit0 */
	U8 RXOW_EN:1;		/* bit1 */
	U8 reserved:1;		/* bit2 */
	U8 FAST_TURN_EN:1;	/* bit3 */
	U8 HILO:1;			/* bit4 */
	U8 ATT:1;			/* bit5 */
	U8 LNA:1;			/* bit6 */
	U8 AGC_EN:1;		/* bit7 */
}struct_cyrf6936_reg_rx_cfg_adr;
typedef union tag_union_cyrf6936_reg_rx_cfg_adr {
	U8 byte;
	struct_cyrf6936_reg_rx_cfg_adr bits;
}union_cyrf6936_reg_rx_cfg_adr;										/* 0x06, rx_cfg_adr */
typedef struct tag_struct_cyrf6936_reg_rx_irq_status_adr {
	U8 RXE_IRQ:1;		/* bit0 */
	U8 RXC_IRQ:1;		/* bit1 */
	U8 RXBERR_IRQ:1;	/* bit2 */
	U8 RXB1_IRQ:1;		/* bit3 */
	U8 RXB8_IRQ:1;		/* bit4 */
	U8 RXB16_IRQ:1;		/* bit5 */
	U8 SOFDET_IRQ:1;	/* bit6 */
	U8 RXOW_IRQ:1;		/* bit7 */
}struct_cyrf6936_reg_rx_irq_status_adr;
typedef union tag_union_cyrf6936_reg_rx_irq_status_adr {
	U8 byte;
	struct_cyrf6936_reg_rx_irq_status_adr bits;
}union_cyrf6936_reg_rx_irq_status_adr;								/* 0x07, rx_irq_status_adr */
typedef struct tag_struct_cyrf6936_reg_rx_status_adr {
	U8 RX_DATA_MODE:2;	/* bit0..1 */
	U8 RX_CODE:1;	/* bit2 */
	U8 BAD_CRC:1;	/* bit3 */
	U8 CRC0:1;		/* bit4 */
	U8 EOP_ERR:1;	/* bit5 */
	U8 PKT_ERR:1;	/* bit6 */
	U8 RX_ACK:1;	/* bit7 */
}struct_cyrf6936_reg_rx_status_adr;
typedef union tag_union_cyrf6936_reg_rx_status_adr {
	U8 byte;
	struct_cyrf6936_reg_rx_status_adr bits;
}union_cyrf6936_reg_rx_status_adr;									/* 0x08, rx_status_adr */
typedef U8 union_cyrf6936_reg_rx_count_adr;				/* 0x09, rx_count_adr */
typedef U8 union_cyrf6936_reg_rx_length_adr;			/* 0x0a, rx_length_adr */
typedef struct tag_struct_cyrf6936_reg_pwr_ctrl_adr {
	U8 PMU_OUTV:2;	/* bit0..1 */
	U8 LVI_TH:2;	/* bit2..3 */
	U8 reserved:1;	/* bit4 */
	U8 PMU_SEN:1;	/* bit5 */
	U8 LVIRQ_EN:1;	/* bit6 */
	U8 PMU_EN:1;	/* bit7 */
}struct_cyrf6936_reg_pwr_ctrl_adr;
typedef union tag_union_cyrf6936_reg_pwr_ctrl_adr {
	U8 byte;
	struct_cyrf6936_reg_pwr_ctrl_adr bits;
}union_cyrf6936_reg_pwr_ctrl_adr;									/* 0x0b, pwr_ctrl_adr */
typedef struct tag_struct_cyrf6936_reg_xtal_ctrl_adr {
	U8 FREQ:3;		/* bit0..2 */
	U8 reserved:2;	/* bit3..4 */
	U8 XSIRQ_EN:1;	/* bit5 */
	U8 XOUT_FN:2;	/* bit6..7 */
}struct_cyrf6936_reg_xtal_ctrl_adr;
typedef union tag_union_cyrf6936_reg_xtal_ctrl_adr {
	U8 byte;
	struct_cyrf6936_reg_xtal_ctrl_adr bits;
}union_cyrf6936_reg_xtal_ctrl_adr;									/* 0x0c, xtal_ctrl_adr */
typedef struct tag_struct_cyrf6936_reg_io_cfg_adr {
	U8 IRQ_GPIO:1;		/* bit0 */
	U8 SPI3PIN:1;		/* bit1 */
	U8 PACTL_GPIO:1;	/* bit2 */
	U8 PACTL_OD:1;		/* bit3 */
	U8 XOUT_OD:1;		/* bit4 */
	U8 MISO_OD:1;		/* bit5 */
	U8 IRQ_POL:1;		/* bit6 */
	U8 IRQ_OD:1;		/* bit7 */
}struct_cyrf6936_reg_io_cfg_adr;
typedef union tag_union_cyrf6936_reg_io_cfg_adr {
	U8 byte;
	struct_cyrf6936_reg_io_cfg_adr bits;
}union_cyrf6936_reg_io_cfg_adr;										/* 0x0d, io_cfg_adr */
typedef struct tag_struct_cyrf6936_reg_gpio_ctrl_adr {
	U8 IRQ_IP:1;	/* bit0 */
	U8 PACTL_IP:1;	/* bit1 */
	U8 MISO_IP:1;	/* bit2 */
	U8 XOUT_IP:1;	/* bit3 */
	U8 IRQ_OP:1;	/* bit4 */
	U8 PACTL_OP:1;	/* bit5 */
	U8 MISO_OP:1;	/* bit6 */
	U8 XOUT_OP:1;	/* bit7 */
}struct_cyrf6936_reg_gpio_ctrl_adr;
typedef union tag_union_cyrf6936_reg_gpio_ctrl_adr {
	U8 byte;
	struct_cyrf6936_reg_gpio_ctrl_adr bits;
}union_cyrf6936_reg_gpio_ctrl_adr;									/* 0x0e, gpio_ctrl_adr */
typedef struct tag_struct_cyrf6936_reg_xact_cfg_adr {
	U8 ACK_TO:2;	/* bit0..1 */
	U8 END_STATE:3;	/* bit2..4 */
	U8 FRC_END:1;	/* bit5 */
	U8 reserved:1;	/* bit6 */
	U8 ACK_EN:1;	/* bit7 */
}struct_cyrf6936_reg_xact_cfg_adr;
typedef union tag_union_cyrf6936_reg_xact_cfg_adr {
	U8 byte;
	struct_cyrf6936_reg_xact_cfg_adr bits;
}union_cyrf6936_reg_xact_cfg_adr;									/* 0x0f, xact_cfg_adr */
typedef struct tag_struct_cyrf6936_reg_framing_cfg_adr {
	U8 SOP_TH:5;	/* bit0..4 */
	U8 LEN_EN:1;	/* bit5 */
	U8 SOP_LEN:1;	/* bit6 */
	U8 SOP_EN:1;	/* bit7 */
}struct_cyrf6936_reg_framing_cfg_adr;