lan9118.h

2410平台vxworks下的lan9118驱动。

#ifdef __cplusplus
extern "C" {
#endif

#ifndef ____LAN9118REG_H____
#define ____LAN9118REG_H____

#ifndef U32
#define U32 unsigned int
#endif
#ifndef S32
#define S32 int
#endif
#ifndef U16
#define U16 unsigned short
#endif
#ifndef S16
#define S16 short
#endif
#ifndef U8
#define U8  unsigned char
#endif
#ifndef S8
#define S8  char
#endif

#include <vxWorks.h>
#include <taskLib.h>
#include <stdio.h>
#include <string.h>


/* align 4byte */
#define LAN9118CS_BASE (0x28000000)

/* TX and RX FIFO port */
#define LAN9118_REG_OFFSET_RX_DATA (0x00000000)
#define LAN9118_REG_OFFSET_TX_DATA (0x00000020)
#define LAN9118_REG_OFFSET_RX_STATUS (0x00000040)
#define LAN9118_REG_OFFSET_TX_STATUS (0x00000048)

/* system control and status register */
#define LAN9118_REG_OFFSET_ID_REV (0x00000050)
#define LAN9118_REG_OFFSET_IRQ_CFG (0x00000054)
#define LAN9118_REG_OFFSET_INT_STS (0x00000058)
#define LAN9118_REG_OFFSET_INT_EN (0x0000005c)
#define LAN9118_REG_OFFSET_BYTE_TEST (0x00000064)
#define LAN9118_REG_OFFSET_FIFO_INT (0x00000068)
#define LAN9118_REG_OFFSET_RX_CFG (0x0000006c)
#define LAN9118_REG_OFFSET_TX_CFG (0x00000070)
#define LAN9118_REG_OFFSET_HW_CFG (0x00000074)
#define LAN9118_REG_OFFSET_RX_DP_CTL (0x00000078)
#define LAN9118_REG_OFFSET_RX_FIFO_INF (0x0000007c)
#define LAN9118_REG_OFFSET_TX_FIFO_INF (0x00000080)
#define LAN9118_REG_OFFSET_PMT_CTRL (0x00000084)
#define LAN9118_REG_OFFSET_GPIO_CFG (0x00000088)
#define LAN9118_REG_OFFSET_GPT_CFG (0x0000008c)
#define LAN9118_REG_OFFSET_GPT_CNT (0x00000090)
#define LAN9118_REG_OFFSET_ENDIAN (0x00000098)
#define LAN9118_REG_OFFSET_FREE_RUN (0x0000009c)
#define LAN9118_REG_OFFSET_RX_DROP (0x000000a0)
#define LAN9118_REG_OFFSET_MAC_CSR_CMD (0x000000a4)
#define LAN9118_REG_OFFSET_MAC_CSR_DATA (0x000000a8)
#define LAN9118_REG_OFFSET_AFC_CFG (0x000000ac)
#define LAN9118_REG_OFFSET_E2P_CMD (0x000000b0)
#define LAN9118_REG_OFFSET_E2P_DATA (0x000000b4)

/* MAC control and status registers */
#define LAN9118_REG_SUBOFFSET_MAC_CR (0x1)
#define LAN9118_REG_SUBOFFSET_ADDRH (0x2)
#define LAN9118_REG_SUBOFFSET_ADDRL (0x3)
#define LAN9118_REG_SUBOFFSET_HASHH (0x4)
#define LAN9118_REG_SUBOFFSET_HASHL (0x5)
#define LAN9118_REG_SUBOFFSET_MII_ACC (0x6)
#define LAN9118_REG_SUBOFFSET_MII_DATA (0x7)
#define LAN9118_REG_SUBOFFSET_FLOW (0x8)
#define LAN9118_REG_SUBOFFSET_VLAN1 (0x9)
#define LAN9118_REG_SUBOFFSET_VLAN2 (0xa)
#define LAN9118_REG_SUBOFFSET_WUFF (0xb)
#define LAN9118_REG_SUBOFFSET_WUCSR (0xc)

/* PHY control and status registers */
#define LAN9118_REG_SUBOFFSET_Basic_Control_Register (0x0)
#define LAN9118_REG_SUBOFFSET_Basic_Status_Register (0x1)
#define LAN9118_REG_SUBOFFSET_PHY_Identifier1 (0x2)
#define LAN9118_REG_SUBOFFSET_PHY_Identifier2 (0x3)
#define LAN9118_REG_SUBOFFSET_Auto_Negotiation_Advertisement_Register (0x4)
#define LAN9118_REG_SUBOFFSET_Auto_Negotiation_Link_Partner_Ability_Register (0x5)
#define LAN9118_REG_SUBOFFSET_Auto_Negotiation_Expansion_Register (0x6)
#define LAN9118_REG_SUBOFFSET_Mode_Control_Status_Register (0x11)
#define LAN9118_REG_SUBOFFSET_Special_Modes_Register (0x12)
#define LAN9118_REG_SUBOFFSET_Special_Control_Status_Indications (0x1b)
#define LAN9118_REG_SUBOFFSET_Interrupt_Source_Register (0x1d)
#define LAN9118_REG_SUBOFFSET_Interrupt_Mask_Register (0x1e)
#define LAN9118_REG_SUBOFFSET_PHY_Special_Control_Status_Register (0x1f)

/*********************************************************/
#define LAN9118_REG_ID_REV_ID_MASK  (0xffff0000)
#define LAN9118_REG_ID_REV_REV_MASK  (0x0000ffff)
#define LAN9118_REG_ID_REV_VALUE (0x01180000)
#define LAN9218_REG_ID_REV_VALUE (0x118a0000)

/*****************/
#define LAN9118_MAC_TIMEOUT (200)
#define LAN9118_PHY_TIMEOUT (200)

/* vxWorks interrupt vector */
#define LAN9118_INT_LEVEL (0)
#define LAN9118_INT_VECTOR (LAN9118_INT_LEVEL)

/* lan9118 tx/rx command word */
typedef struct tag_struct_tx_command_a{
    U32 buffer_size:11;
    U32 reserved11:1;
    U32 last_segment:1;
    U32 first_segment:1;
    U32 reserved14_15:2;
    U32 data_start_offset:5;
    U32 reserved21_23:3;
    U32 buffer_end_alignment:2;
    U32 reserved26_30:5;
    U32 interrupt_on_completion:1;
}struct_tx_command_a;
typedef union tag_union_tx_command_a {
    struct_tx_command_a bits;
    U32 data;
}union_tx_command_a;

typedef struct tag_struct_tx_command_b{
    U32 package_length:11;
    U32 reserved11:1;
    U32 disable_padding:1;
    U32 crc_disable:1;
    U32 reserved14_15:2;
    U32 package_tag:16;
}struct_tx_command_b;
typedef union tag_union_tx_command_b {
    struct_tx_command_b bits;
    U32 data;
}union_tx_command_b;

/* lan9118 tx/rx status word */
typedef struct tag_struct_tx_status {
    U32 deferred:1;
    U32 underrun_error:1;
    U32 excessive_deferral:1;
    U32 collision_count:4;
    U32 reserved_7:1;
    U32 excessive_collision:1;
    U32 late_collision:1;
    U32 no_carrier:1;
    U32 loss_of_carrier:1;
    U32 reserved_12_14:3;
    U32 error_status:1;
    U32 package_tag:16;
}struct_tx_status;
typedef union tag_union_tx_status {
    struct_tx_status bits;
    U32 data;
}union_tx_status;

typedef struct tag_struct_rx_status {
    U32 reserved0:1;
    U32 crc_error:1;
    U32 dribbling_bit:1;
    U32 mii_error:1;
    U32 receive_watchdog_time_out:1;
    U32 frame_type:1;
    U32 collision_seen:1;
    U32 frame_too_long:1;
    U32 reserved8_9:2;
    U32 multicast_frame:1;
    U32 runt_frame:1;
    U32 length_error:1;
    U32 broadcast_frame:1;
    U32 reserved14:1;
    U32 error_status:1;
    U32 package_length:14;
    U32 filtering_fail:1;
    U32 reserved31:1;
}struct_rx_status;
typedef union tag_union_rx_status {
    struct_rx_status bits;
    U32 data;
}union_rx_status;

#endif

#ifdef __cplusplus
}
#endif