📄 periph.lst
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C51 COMPILER V7.10 PERIPH 05/28/2007 19:12:34 PAGE 1
C51 COMPILER V7.10, COMPILATION OF MODULE PERIPH
OBJECT MODULE PLACED IN .\_Oput\periph.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE source\periph.c ROM(COMPACT) OPTIMIZE(9,SPEED) BROWSE ORDER DEFINE(GPIF=0,F
-LASH=0,DEVICE_TYPE_IS_SCSI=1,DEVICE_TYPE_IS_IDE=1,VBUS_DETECT=1) DEBUG OBJECTEXTEND CODE PRINT(.\_List\periph.lst) OBJEC
-T(.\_Oput\periph.obj)
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: periph.c
4 // Contents: Hooks required to implement USB peripheral function.
5 //
6 // Copyright (c) 1997 AnchorChips, Inc. All rights reserved
7 //
8 // $Archive: /USB/atapifx2/software/periph.c $
9 // $Date: 1/23/02 9:36a $
10 // $Revision: 58 $
11 //-----------------------------------------------------------------------------
12 #include "fx2.h"
13 #include "fx2regs.h"
14 #include "gpif.h"
15 #include "atapi.h"
16
17 extern BOOL Sleep;
18 extern BOOL Rwuen;
19 extern BOOL Selfpwr;
20
21 void clearResetLine();
22 void clearResetLine();
23
24 WORD cbwTagLow; // Tag from the most recent CBW packet
25 WORD cbwTagHi;
26 BYTE currentState;
27
28 DWORD dataTransferLen;
29 DWORD driveCapacity;
30 bit scsi;
31
32 BYTE xdata SCSIInquiryData[44];
33 BYTE code SCSIInquiryDataSource[44] =
34 {
35 0x00, //= Device class
36 //0x0e, // Device class RBC
37 0x00, //= RMB bit is set by inquiry data
38 0x00, //
39 0x01, //= Data format = 1
40 0x00, //= Additional length (changed to 0 from 0x75)
41 0x00, 0x00, 0x00, //
42 0x43, 0x79, 0x70, 0x72, 0x65, 0x73, 0x73, 0x20, // = Manufacturer "Cypress "
43 0x41, 0x54, 0x41, 0x50, 0x49, 0x20, 0x52, 0x65, 0x66, 0x20, 0x44, 0x65, 0x73, 0x69, 0x67, 0x6e, // = Produ
-ct(MS Ref Design)
44 0x30, 0x31, 0x2E, 0x30, // = Revision
45 0x30, 0x39, 0x2F, 0x32, 0x34, 0x2F, 0x39, 0x38, // = Vendor unique (chopped off)
46
47 };
48
49 //-----------------------------------------------------------------------------
50 // Task Dispatcher hooks
51 // The following hooks are called by the task dispatcher.
52 //-----------------------------------------------------------------------------
C51 COMPILER V7.10 PERIPH 05/28/2007 19:12:34 PAGE 2
53
54 void TD_Init(void) // Called once at startup
55 {
56 1 // set the CPU clock to 48MHz
57 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
58 1 WRITEDELAY();
59 1
60 1 // set the slave FIFO interface to 48MHz
61 1 IFCONFIG |= 0x40;
62 1 WRITEDELAY();
63 1
64 1 // init state/reset variables
65 1 currentState = UNCONFIGURED;
66 1
67 1 initUSB(); // configure output ports and endpoint params
68 1 mymemmovexx(&GPIF_WAVE_DATA, (BYTE xdata *) WaveDataPio0, 64); // load wave forms in memory
69 1 mymemmovexx(SCSIInquiryData, (BYTE xdata *) SCSIInquiryDataSource, sizeof(SCSIInquiryDataSource));
70 1
71 1 resetATAPIDevice();
72 1
73 1 if (SCSITestUnitReady())
74 1 SCSITestUnitReady();
75 1
76 1
77 1 ATAPIIdDevice(); // Get serial number
78 1
79 1 if (SCSITestUnitReady())
80 1 SCSITestUnitReady();
81 1
82 1 intrfcSubClass = USB_MS_SCSI_TRANSPARENT_SUBCLASS; // IDE devices are treated as transparent SCSI. No
-rmally would use RBC, but it's not in Microsoft's INF file.
83 1 if (scsi)
84 1 {
85 2 SCSIInquiryToATAPI(); // Set intrfcSubClass to tell Zip and MO from CD-ROM
86 2 }
87 1 }
88
89
90 char const code usbcString[] = "USBC";
91 void TD_Poll(void) // Called repeatedly while the device is idle
92 {
93 1 WORD count = 0;
94 1
95 1 // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
96 1 if(!(EP2CS & bmEPEMPTY))
97 1 {
98 2 // Check for "USBC"
99 2 if ( *((DWORD xdata *)EP2FIFOBUF) != *((DWORD xdata *) usbcString))
100 2 {
101 3 // error -- Stall the endpoint no matter what
102 3 EP2CS = bmEPSTALL;
103 3 }
104 2 else
105 2 {
106 3 if (EP2BC < EP2FIFOBUF[CBW_CBW_LEN]+CBW_DATA_START)
107 3 {
108 4 // Error -- Stall the endpoint
109 4 EP2CS = bmEPSTALL;
110 4 }
111 3 else
112 3 {
113 4 // Good packet, forward to the device.
C51 COMPILER V7.10 PERIPH 05/28/2007 19:12:34 PAGE 3
114 4 processCBW();
115 4 }
116 3 }
117 2 }
118 1 }
119
120
121 //-----------------------------------------------------------------------------
122 // Support functions for specific device
123 //-----------------------------------------------------------------------------
124
125 void initUSB(void)
126 {
127 1
128 1 PORTACFG = 0x01; // set up PORTA for port I/O
129 1 OEA = 0xBE; // PORTA is all output except PA.0(INTRQ) AND PA.6(DASP#)
130 1 OUTATAPI = ATAPI_IDLE_VALUE; // includes RESET line PA.0
131 1
132 1 // Make Interrupt 0 level triggered
133 1 IT0 = 0;
134 1
135 1 //CPUCS = 0x0c; // set clock to 24MHz.
136 1 IFCONFIG = 0x8A | bmGSTATE; // b7=0: use FCLK pin to clock FIFO, GPIF; =1: use internal 30/48 MHz
-clock(=30)
137 1 CPUCS = 0x14; // set clock to 48MHz.
138 1 //IFCONFIG = 0xcA; // b7=0: use FCLK pin to clock FIFO, GPIF; =1: use internal 30/48 MHz clock(=48
-)
139 1 FIFOPINPOLAR = 0x00; // ff pin is active low
140 1
141 1 PINFLAGSAB = 0x00; // FLAGA PF for FIFO selected by FIFOADR[1..0]
142 1 PINFLAGSCD = 0x00; // FLAGB FF for FIFO selected by FIFOADR[1..0]
143 1
144 1 // Set up interrupt parameter
145 1 // INTSETUP |= bmINT4; // Allow FIFO and GPIF interrupts
146 1
147 1 // GPIF and CTL configuration
148 1 GPIFCTLCFG = 0x00; //
149 1 GPIFIDLECTL = 0x77; // x111x111 - CTL3 not enabled
150 1 // ||||||||_CTL0 = 1 during idle
151 1 // |||||||__CTL1 = 1 during idle
152 1 // ||||||___CTL2 = 1 during idle
153 1 // ||||_____CTL0 output enable
154 1 // |||______CTL1 output enable
155 1 // ||_______CTL2 output enable
156 1 //
157 1 GPIFIDLECS = 0; // tristate data bus during idle interval
158 1 GPIFWFSELECT = (2 << 6) | (3 << 4) | (0 << 2) | (1); // Single write is 2, Single read is 3, write i
-s 0, Read is waveform 1
159 1
160 1 // Endpoint initialization
161 1 EP2CFG = 0xA0; // ep2 is valid BULK OUT 512 quad buffered
162 1 EP2FIFOCFG = 0x05; // WORDWIDE=1M MANUAL
163 1 EP2FIFOPFH = 0x00; // PF=0 when BC > PF -> Decis=0 (1 byte in FIFO)
164 1 EP2FIFOPFL = 0x00; // PF and BC refer to the current pkt -> PKTSTAT=0
165 1 EP2GPIFPFSTOP = 0; // Do not stop on PF
166 1
167 1 EP8CFG = 0xE0; // ep8 is valid BULK IN 512 double buffered
168 1 EP8FIFOCFG = 0x05; // set EP8: 0x05=MANUAL, 0x0D=AUTOIN
169 1
170 1 // mark all unused endpoints invalid - setting each reg to 0x22 instead of just clearing
171 1 // the valid bit to save code space. 0x22 basically sets all of these endpoints to
172 1 // not valid, bulk, double 512 buffered.
C51 COMPILER V7.10 PERIPH 05/28/2007 19:12:34 PAGE 4
173 1 EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = 0x22;
174 1
175 1 // disbable Auto Arm
176 1 REVCTL |= bmNOAUTOARM;
177 1
178 1 // arm the OUT endpoint. By default OUT endpoints come up unarmed.
179 1 ResetAndArmEp2();
180 1
181 1 }
182
183
184
185 // Stalls EP2OUT endpoint.
186 void stallEP2OUT()
187 {
188 1 // Check to see if stall is needed. If it is, STALL the endpoint.
189 1 // After we have set the STALL, make sure we didn't get the last packet while we were STALLing.
190 1 WORD x;
191 1
192 1 if (EP2468STAT & bmEP2EMPTY)
193 1 x = 0;
194 1 else
195 1 x = EP2FIFOBCL + (EP2FIFOBCH << 8) + EP2BC;
196 1
197 1 // if (dataTransferLen > ((x + 1) & 0xfffe)) // Round up to allow for odd xfer lengths
198 1 if (dataTransferLen > x)
199 1
200 1 {
201 2 EP2CS |= bmEPSTALL;
202 2
203 2 EZUSB_Delay(100);
204 2
205 2 if (EP2CS & bmEPSTALL)
206 2 x=1234;
207 2
208 2 // If the host has already cleared the STALL, the EP will be empty here, but we will drop safely thr
-ough the if()
209 2 if (EP2468STAT & bmEP2EMPTY)
210 2 x = 0;
211 2 else
212 2 x = EP2FIFOBCL + (EP2FIFOBCH << 8) + EP2BC;
213 2
214 2 if (dataTransferLen > x)
215 2 {
216 3 ResetAndArmEp2(); // Stall no longer needed
217 3 EP2CS = 0; // Clear stall bit
218 3 }
219 2 }
220 1 }
221
222 void processCBW()
223 {
224 1 // Save the tag for use in the response
225 1 cbwTagLow = *((WORD volatile xdata*)(EP2FIFOBUF+CBW_TAG));
226 1 cbwTagHi = *((WORD volatile xdata*)(EP2FIFOBUF+CBW_TAG+2));
227 1
228 1 // Get the length (convert from little endian)
229 1 *(((BYTE *) &dataTransferLen)+3) = (EP2FIFOBUF+CBW_DATA_TRANSFER_LEN_LSB)[0]; // "Residue"
230 1 *(((BYTE *) &dataTransferLen)+2) = (EP2FIFOBUF+CBW_DATA_TRANSFER_LEN_LSB)[1]; // "Residue"
231 1 *(((BYTE *) &dataTransferLen)+1) = (EP2FIFOBUF+CBW_DATA_TRANSFER_LEN_LSB)[2]; // "Residue"
232 1 *(((BYTE *) &dataTransferLen)+0) = (EP2FIFOBUF+CBW_DATA_TRANSFER_LEN_LSB)[3]; // "Residue"
233 1
C51 COMPILER V7.10 PERIPH 05/28/2007 19:12:34 PAGE 5
234 1 // writePIO8(ATAPI_NULL_REG, dataTransferLenLSW);
235 1
236 1 // Our personal "firmware update" command
237 1 if (EP2FIFOBUF[0xf] == 0xfb && !(EP2FIFOBUF[CBW_FLAGS] & CBW_FLAGS_DIR_BIT))
238 1 {
239 2 // relinquish control of the bulk buffer occupied by the CBW
240 2 EP2BCL = 0x80;
241 2
242 2 // Write the EEPROM
243 2 // EEPROMWrite(dataTransferLenLSW);
244 2 sendUSBS(USBS_PASSED);
245 2 }
246 1 else if (EP2FIFOBUF[0xf] == 0xfa && (EP2FIFOBUF[CBW_FLAGS] & CBW_FLAGS_DIR_BIT))
247 1 {
248 2 extern BYTE code StringDscr3;
249 2 BYTE len = (&StringDscr3)[0]<<1;
250 2
251 2 len = max(len, dataTransferLenLSW);
252 2
253 2 // relinquish control of the bulk buffer occupied by the CBW
254 2 EP2BCL = 0x80;
255 2
256 2 mymemmovexx(EP8FIFOBUF, (char xdata *)(&StringDscr3)+2, len);
257 2 waitForInBuffer();
258 2 EP8BCH = 0;
259 2 EP8BCL = len;
260 2 sendUSBS(USBS_PASSED);
261 2 }
262 1 else if (EP2FIFOBUF[CBW_FLAGS] & CBW_FLAGS_DIR_BIT || !dataTransferLen)
263 1 {
264 2 currentState = RECEIVED_IN_CMD;
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