📄 gpif.lst
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231 1
232 1 while (!gpifIdle());
233 1
234 1 GPIFWFSELECT = (1 << 4); // PIO read is waveform 1
235 1
236 1 // put out address of interest
237 1 OUTATAPI = addr | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
238 1
239 1 // trigger the GPIF
C51 COMPILER V7.10 GPIF 05/28/2007 19:12:30 PAGE 5
240 1 retval = XGPIFSGLDATLX; // Single bus transaction on the GPIF
241 1
242 1 while (!gpifIdle()); // wait till GPIF is done before getting real data
243 1
244 1 retval = (XGPIFSGLDATLNOX << 8) + XGPIFSGLDATH; // get data from last GPIF transaction
245 1 OUTATAPI = ATAPI_IDLE_VALUE; // Clear the address/chip selects
246 1
247 1 return(retval);
248 1 }
249
250
251 // Read a string from the given disk register or buffer
252 void readPIO16(char addr, WORD count)
253 {
254 1 // check for GPIF ready
255 1 while (!gpifIdle());
256 1
257 1 GPIFWFSELECT = (1); // PIO read is waveform 1
258 1
259 1 // Write the address/chip selects
260 1 OUTATAPI = addr | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
261 1
262 1 // set up for GPIF transfer - wordwide, so count/2
263 1 EP8GPIFTCH = MSB(count >> 1);
264 1 EP8GPIFTCL = LSB(count >> 1);
265 1
266 1 // trigger GPIF. No longer wait 'til done
267 1 GPIFTRIG = 0x07; // GPIFTRIG[2] = RD/WR BIT (1 = READ)
268 1 // GPIFTRIG[1..0] = EP#, 00=ep2, 01=ep4, 10 = ep6, 11=ep8
269 1
270 1 }
271
272 // read count WORDs using UDMA
273 void readUDMA(DWORD count)
274 {
275 1 // check for GPIF ready
276 1 while (!gpifIdle());
277 1
278 1 GPIFWFSELECT = (3); // UDMA read is waveform 3
279 1
280 1 // Write the address/chip selects -- Note that this is not the same register as the ATAPI_DATA_REG
281 1 OUTATAPI = CS(3) | DA(0) | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
282 1
283 1 // set up for GPIF transfer - wordwide
284 1 GPIFTCB3 = 0;
285 1 GPIFTCB2 = ((BYTE *) &count)[1];
286 1 GPIFTCB1 = ((BYTE *) &count)[2];
287 1 GPIFTCB0 = LSB(count);
288 1
289 1 FLOWSTATE = 0x82;
290 1
291 1 // trigger GPIF and wait till done
292 1 GPIFTRIG = 0x07; // GPIFTRIG[2] = RD/WR BIT (1 = READ)
293 1 // GPIFTRIG[1..0] = EP#, 00=ep2, 01=ep4, 10 = ep6, 11=ep8
294 1
295 1 // Wait for the drive interrupt.
296 1 while(!(IOA & 0x01));
297 1
298 1 if (!gpifIdle())
299 1 {
300 2 abortGPIF();
301 2 }
C51 COMPILER V7.10 GPIF 05/28/2007 19:12:30 PAGE 6
302 1
303 1 FLOWSTATE = 0x00;
304 1 }
305
306 // Wait for all of the bulk buffers to be full (or all of the data to be received)
307 // Switch to manual mode
308 // Write count WORDs using UDMA
309 // Return drive status
310 void writeUDMA(DWORD count)
311 {
312 1 BYTE drvstat=0;
313 1 WORD byteCount;
314 1 BYTE i;
315 1
316 1 // Special code for switching between auto/manual modes. Make sure that all of
317 1 // the buffers are full before switching.
318 1 for (i = 0, byteCount = 0; i < 4 && byteCount < dataTransferLen; i++, byteCount +=wPacketSize)
319 1 {
320 2 // wait for the sector to show up
321 2 while ((EP2CS & bmEPEMPTY))
322 2 ;
323 2
324 2 // commit the buffer(s) to the GPIF
325 2 EP2BCL = 0x00;
326 2 WRITEDELAY();
327 2 }
328 1
329 1 initUdmaWrite();
330 1
331 1 EP2FIFOCFG = bmAUTOOUT | bmWORDWIDE;
332 1
333 1 // check for GPIF ready
334 1 while (!gpifIdle());
335 1
336 1 GPIFWFSELECT = (2 << 2); // UDMA write is waveform 2
337 1
338 1 // Write the address/chip selects -- Note that this is not the same register as the ATAPI_DATA_REG
339 1 OUTATAPI = CS(3) | DA(0) | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
340 1
341 1 // set up for GPIF transfer - wordwide
342 1 GPIFTCB3 = 0;
343 1 GPIFTCB2 = ((BYTE *) &count)[1];
344 1 GPIFTCB1 = ((BYTE *) &count)[2];
345 1 GPIFTCB0 = LSB(count);
346 1
347 1 FLOWSTATE = 0x83;
348 1
349 1 // trigger GPIF and wait till done
350 1 EP2GPIFTRIG = 0;
351 1
352 1 // Wait for the drive interrupt.
353 1 while( !((drvstat = IOA) & 0x01))
354 1 ;
355 1
356 1 if (!gpifIdle())
357 1 {
358 2 abortGPIF();
359 2 }
360 1
361 1 FLOWSTATE = 0x00;
362 1
363 1 // cancel AUTO OUT mode
C51 COMPILER V7.10 GPIF 05/28/2007 19:12:30 PAGE 7
364 1 EP2FIFOCFG = bmWORDWIDE;
365 1 WRITEDELAY();
366 1 }
367
368 void abortGPIF()
369 {
370 1 FLOWSTATE = 0x00; // xro - take out of UDMA flowstate
371 1 GPIFABORT = 0xff;
372 1
373 1 // reset the transaction count state machine, in FX2 revs up to and
374 1 // including Rev D, there is a bug that prevents the GPIF state machine
375 1 // from properly reseting following an abort. The following code is a
376 1 // workaround for this problem. See the FX2 chip errata for details.
377 1 #ifdef GPIF_ABORT_BUG_PRESENT
mymemmovexx(&GPIF_WAVE_DATA, (BYTE xdata *) AbortWave, sizeof(WaveDataPio4));
GPIFWFSELECT = 0; // PIO write is waveform 0
EP2GPIFTCH = 0;
EP2GPIFTCL = 1;
GPIFSGLDATLX = 0;
mymemmovexx(&GPIF_WAVE_DATA, (BYTE xdata *) WaveDataPio4, sizeof(WaveDataPio4));
#endif
388 1 }
389
C51 COMPILER V7.10 GPIF 05/28/2007 19:12:30 PAGE 8
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION hardwareReset (BEGIN)
; SOURCE LINE # 104
; SOURCE LINE # 105
; SOURCE LINE # 106
0000 53807F ANL IOA,#07FH
; SOURCE LINE # 107
0003 7F64 MOV R7,#064H
0005 7E00 MOV R6,#00H
0007 120000 E LCALL _EZUSB_Delay
; SOURCE LINE # 108
000A 438080 ORL IOA,#080H
; SOURCE LINE # 109
000D 22 RET
; FUNCTION hardwareReset (END)
; FUNCTION initUdmaRead (BEGIN)
; SOURCE LINE # 112
; SOURCE LINE # 113
; SOURCE LINE # 115
0000 90E6C7 MOV DPTR,#0E6C7H
0003 7436 MOV A,#036H
0005 F0 MOVX @DPTR,A
; SOURCE LINE # 116
0006 A3 INC DPTR
0007 E4 CLR A
0008 F0 MOVX @DPTR,A
; SOURCE LINE # 117
0009 A3 INC DPTR
000A 7402 MOV A,#02H
000C F0 MOVX @DPTR,A
; SOURCE LINE # 118
000D 90E6CB MOV DPTR,#0E6CBH
0010 74D0 MOV A,#0D0H
0012 F0 MOVX @DPTR,A
; SOURCE LINE # 119
0013 A3 INC DPTR
0014 7403 MOV A,#03H
0016 F0 MOVX @DPTR,A
; SOURCE LINE # 120
0017 90E60C MOV DPTR,#0E60CH
001A 7401 MOV A,#01H
001C F0 MOVX @DPTR,A
; SOURCE LINE # 122
001D 90E61B MOV DPTR,#0E61BH
0020 740D MOV A,#0DH
0022 F0 MOVX @DPTR,A
; SOURCE LINE # 123
0023 90E601 MOV DPTR,#0E601H
0026 74C6 MOV A,#0C6H
0028 F0 MOVX @DPTR,A
; SOURCE LINE # 124
0029 22 RET
; FUNCTION initUdmaRead (END)
; FUNCTION initUdmaWrite (BEGIN)
; SOURCE LINE # 126
; SOURCE LINE # 127
; SOURCE LINE # 128
0000 90E6C7 MOV DPTR,#0E6C7H
C51 COMPILER V7.10 GPIF 05/28/2007 19:12:30 PAGE 9
0003 7470 MOV A,#070H
0005 F0 MOVX @DPTR,A
; SOURCE LINE # 129
0006 A3 INC DPTR
0007 E4 CLR A
0008 F0 MOVX @DPTR,A
; SOURCE LINE # 130
0009 A3 INC DPTR
000A 7408 MOV A,#08H
000C F0 MOVX @DPTR,A
; SOURCE LINE # 131
000D 90E6CB MOV DPTR,#0E6CBH
0010 7411 MOV A,#011H
0012 F0 MOVX @DPTR,A
; SOURCE LINE # 132
0013 A3 INC DPTR
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