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; IPC9 : Interrupt Priority Control Register 9
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv C2IP2, 0x000A
.equiv C2IP1, 0x0009
.equiv C2IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv INT4IP2, 0x0006
.equiv INT4IP1, 0x0005
.equiv INT4IP0, 0x0004
.equiv INT3IP2, 0x0002
.equiv INT3IP1, 0x0001
.equiv INT3IP0, 0x0000
;------------------------------------------------------------------------------
; IPC10 : Interrupt Priority Control Register 10
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv LVDIP2, 0x000A
.equiv LVDIP1, 0x0009
.equiv LVDIP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv DCIIP2, 0x0006
.equiv DCIIP1, 0x0005
.equiv DCIIP0, 0x0004
;==============================================================================
;
; 3. Input Change Notification Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 3a. SFR Definitions
;------------------------------------------------------------------------------
.equiv CNEN1L, _CNEN1 ; See description for all
.equiv CNEN1H, _CNEN1+1 ; registers in sub-section below
.equiv CNEN2L, _CNEN2
.equiv CNEN2H, _CNEN2+1
.equiv CNPU1L, _CNPU1
.equiv CNPU1H, _CNPU1+1
.equiv CNPU2L, _CNPU2
.equiv CNPU2H, _CNPU2+1
;------------------------------------------------------------------------------
; 3b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; CNEN1 : Input Change Notification Interrupt Enable Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CN15IE, 0x000F
.equiv CN14IE, 0x000E
.equiv CN13IE, 0x000D
.equiv CN12IE, 0x000C
.equiv CN11IE, 0x000B
.equiv CN10IE, 0x000A
.equiv CN9IE, 0x0009
.equiv CN8IE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN7IE, 0x0007
.equiv CN6IE, 0x0006
.equiv CN5IE, 0x0005
.equiv CN4IE, 0x0004
.equiv CN3IE, 0x0003
.equiv CN2IE, 0x0002
.equiv CN1IE, 0x0001
.equiv CN0IE, 0x0000
;------------------------------------------------------------------------------
; CNEN2 : Input Change Notification Interrupt Enable Register 2
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN23IE, 0x0007
.equiv CN22IE, 0x0006
.equiv CN21IE, 0x0005
.equiv CN20IE, 0x0004
.equiv CN19IE, 0x0003
.equiv CN18IE, 0x0002
.equiv CN17IE, 0x0001
.equiv CN16IE, 0x0000
;------------------------------------------------------------------------------
; CNPU1 : Input Change Notification Pullup Enable Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CN15PUE, 0x000F
.equiv CN14PUE, 0x000E
.equiv CN13PUE, 0x000D
.equiv CN12PUE, 0x000C
.equiv CN11PUE, 0x000B
.equiv CN10PUE, 0x000A
.equiv CN9PUE, 0x0009
.equiv CN8PUE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN7PUE, 0x0007
.equiv CN6PUE, 0x0006
.equiv CN5PUE, 0x0005
.equiv CN4PUE, 0x0004
.equiv CN3PUE, 0x0003
.equiv CN2PUE, 0x0002
.equiv CN1PUE, 0x0001
.equiv CN0PUE, 0x0000
;------------------------------------------------------------------------------
; CNPU2 : Input Change Notification Pullup Enable Register 2
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN23PUE, 0x0007
.equiv CN22PUE, 0x0006
.equiv CN21PUE, 0x0005
.equiv CN20PUE, 0x0004
.equiv CN19PUE, 0x0003
.equiv CN18PUE, 0x0002
.equiv CN17PUE, 0x0001
.equiv CN16PUE, 0x0000
;==============================================================================
;
; 4. Timer Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 4a. SFR Definitions
;------------------------------------------------------------------------------
;---------------Timer 1 Module-------------------------------------------------
.equiv TMR1L, _TMR1
.equiv TMR1H, _TMR1+1
.equiv PR1L, _PR1
.equiv PR1H, _PR1+1
.equiv T1CONL, _T1CON ; See TxCON description in
.equiv T1CONH, _T1CON+1 ; sub-section below
;---------------Timer2/3 Module------------------------------------------------
.equiv TMR2L, _TMR2
.equiv TMR2H, _TMR2+1
.equiv TMR3HLDL, _TMR3HLD
.equiv TMR3HLDH, _TMR3HLD+1
.equiv TMR3L, _TMR3
.equiv TMR3H, _TMR3+1
.equiv PR2L, _PR2
.equiv PR2H, _PR2+1
.equiv PR3L, _PR3
.equiv PR3H, _PR3+1
.equiv T2CONL, _T2CON ; See TxCON description in
.equiv T2CONH, _T2CON+1 ; sub-section below
.equiv T3CONL, _T3CON ; - do -
.equiv T3CONH, _T3CON+1
;-------------- Timer4/5 Module------------------------------------------------
.equiv TMR4L, _TMR4
.equiv TMR4H, _TMR4+1
.equiv TMR5HLDL, _TMR5HLD
.equiv TMR5HLDH, _TMR5HLD+1
.equiv TMR5L, _TMR5
.equiv TMR5H, _TMR5+1
.equiv PR4L, _PR4
.equiv PR4H, _PR4+1
.equiv PR5L, _PR5
.equiv PR5H, _PR5+1
.equiv T4CONL, _T4CON ; See TxCON description in
.equiv T4CONH, _T4CON+1 ; sub-section below
.equiv T5CONL, _T5CON ; - do -
.equiv T5CONH, _T5CON+1
;-------------------------------------------------------------------------------
; 4b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; TxCON : Timer x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv TON, 0x000F
.equiv TSIDL, 0x000D
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv TGATE, 0x0006
.equiv TCKPS1, 0x0005
.equiv TCKPS0, 0x0004
.equiv T32, 0x0003 ;T32 present only in T2CON and T4CON
.equiv TSYNC, 0x0002
.equiv TCS, 0x0001
;==============================================================================
;
; 5. Input Capture Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 5a. SFR Definitions
;------------------------------------------------------------------------------
.equiv IC1BUFL, _IC1BUF
.equiv IC1BUFH, _IC1BUF+1
.equiv IC1CONL, _IC1CON ; See ICxCON description in
.equiv IC1CONH, _IC1CON+1 ; sub-section below
.equiv IC2BUFL, _IC2BUF
.equiv IC2BUFH, _IC2BUF+1
.equiv IC2CONL, _IC2CON ; See ICxCON description in
.equiv IC2CONH, _IC2CON+1 ; sub-section below
.equiv IC3BUFL, _IC3BUF
.equiv IC3BUFH, _IC3BUF+1
.equiv IC3CONL, _IC3CON ; See ICxCON description in
.equiv IC3CONH, _IC3CON+1 ; sub-section below
.equiv IC4BUFL, _IC4BUF
.equiv IC4BUFH, _IC4BUF+1
.equiv IC4CONL, _IC4CON ; See ICxCON description in
.equiv IC4CONH, _IC4CON+1 ; sub-section below
.equiv IC5BUFL, _IC5BUF
.equiv IC5BUFH, _IC5BUF+1
.equiv IC5CONL, _IC5CON ; See ICxCON description in
.equiv IC5CONH, _IC5CON+1 ; sub-section below
.equiv IC6BUFL, _IC6BUF
.equiv IC6BUFH, _IC6BUF+1
.equiv IC6CONL, _IC6CON ; See ICxCON description in
.equiv IC6CONH, _IC6CON+1 ; sub-section below
.equiv IC7BUFL, _IC7BUF
.equiv IC7BUFH, _IC7BUF+1
.equiv IC7CONL, _IC7CON ; See ICxCON description in
.equiv IC7CONH, _IC7CON+1 ; sub-section below
.equiv IC8BUFL, _IC8BUF
.equiv IC8BUFH, _IC8BUF+1
.equiv IC8CONL, _IC8CON ; See ICxCON description in
.equiv IC8CONH, _IC8CON+1 ; sub-section below
;------------------------------------------------------------------------------
; 5b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; ICxCON : Input Capture x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv ICSIDL, 0x000D
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv ICTMR, 0x0007
.equiv ICI1, 0x0006
.equiv ICI0, 0x0005
.equiv ICOV, 0x0004
.equiv ICBNE, 0x0003
.equiv ICM2, 0x0002
.equiv ICM1, 0x0001
.equiv ICM0, 0x0000
;==============================================================================
;
; 6. Output Compare Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 6a. SFR Definitions
;------------------------------------------------------------------------------
.equiv OC1RSL, _OC1RS
.equiv OC1RSH, _OC1RS+1
.equiv OC1RL, _OC1R
.equiv OC1RH, _OC1R+1
.equiv OC1CONL, _OC1CON ; See OCxCON description in
.equiv OC1CONH, _OC1CON+1 ; sub-section below
.equiv OC2RSL, _OC2RS
.equiv OC2RSH, _OC2RS+1
.equiv OC2RL, _OC2R
.equiv OC2RH, _OC2R+1
.equiv OC2CONL, _OC2CON ; See OCxCON description in
.equiv OC2CONH, _OC2CON+1 ; sub-section below
.equiv OC3RSL, _OC3RS
.equiv OC3RSH, _OC3RS+1
.equiv OC3RL, _OC3R
.equiv OC3RH, _OC3R+1
.equiv OC3CONL, _OC3CON ; See OCxCON description in
.equiv OC3CONH, _OC3CON+1 ; sub-section below
.equiv OC4RSL, _OC4RS
.equiv OC4RSH, _OC4RS+1
.equiv OC4RL, _OC4R
.equiv OC4RH, _OC4R+1
.equiv OC4CONL, _OC4CON ; See OCxCON description in
.equiv OC4CONH, _OC4CON+1 ; sub-section below
.equiv OC5RSL, _OC5RS
.equiv OC5RSH, _OC5RS+1
.equiv OC5RL, _OC5R
.equiv OC5RH, _OC5R+1
.equiv OC5CONL, _OC5CON ; See OCxCON description in
.equiv OC5CONH, _OC5CON+1 ; sub-section below
.equiv OC6RSL, _OC6RS
.equiv OC6RSH, _OC6RS+1
.equiv OC6RL, _OC6R
.equiv OC6RH, _OC6R+1
.equiv OC6CONL, _OC6CON ; See OCxCON description in
.equiv OC6CONH, _OC6CON+1 ; sub-section below
.equiv OC7RSL, _OC7RS
.equiv OC7RSH, _OC7RS+1
.equiv OC7RL, _OC7R
.equiv OC7RH, _OC7R+1
.equiv OC7CONL, _OC7CON ; See OCxCON description in
.equiv OC7CONH, _OC7CON+1 ; sub-section below
.equiv OC8RSL, _OC8RS
.equiv OC8RSH, _OC8RS+1
.equiv OC8RL, _OC8R
.equiv OC8RH, _OC8R+1
.equiv OC8CONL, _OC8CON ; See OCxCON description in
.equiv OC8CONH, _OC8CON+1 ; sub-section below
;------------------------------------------------------------------------------
; 6b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; OCxCON : Output Compare x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv OCSIDL, 0x000D
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv OCFLT, 0x0004
.equiv OCTSEL, 0x0003
.equiv OCM2, 0x0002
.equiv OCM1, 0x0001
.equiv OCM0, 0x0000
;==============================================================================
;
; 7. Inter-Integrated Circuit(I2C) Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 7a. SFR Definitions
;------------------------------------------------------------------------------
.equiv I2CRCVL, _I2CRCV
.equiv I2CRCVH, _I2CRCV+1
.equiv I2CTRNL, _I2CTRN
.equiv I2CTRNH, _I2CTRN+1
.equiv I2CBRGL, _I2CBRG
.equiv I2CBRGH, _I2CBRG+1
.equiv I2CCONL, _I2CCON ; See I2CCON description in
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