📄 count_10.rpt
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Device-Specific Information: g:\llp\count\count_10.rpt
count_10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\llp\count\count_10.rpt
count_10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CLK
Device-Specific Information: g:\llp\count\count_10.rpt
count_10
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 CLR
Device-Specific Information: g:\llp\count\count_10.rpt
count_10
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
EN : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC7_A5;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = _LC6_A5;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC1_A5;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC1_A4;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC4_A4;
-- Node name is 'L4'
-- Equation name is 'L4', type is output
L4 = _LC3_A4;
-- Node name is 'L5'
-- Equation name is 'L5', type is output
L5 = _LC7_A4;
-- Node name is 'L6'
-- Equation name is 'L6', type is output
L6 = _LC2_A4;
-- Node name is '|count_48:4|7448:3|:69' = '|count_48:4|7448:3|OA'
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ001);
_EQ001 = _LC2_A5 & !_LC3_A5 & _LC4_A5
# _LC2_A5 & _LC4_A5 & !_LC5_A5
# _LC2_A5 & !_LC3_A5 & _LC5_A5
# !_LC3_A5 & !_LC4_A5 & _LC5_A5
# !_LC2_A5 & !_LC3_A5 & !_LC4_A5
# !_LC2_A5 & !_LC4_A5 & !_LC5_A5
# _LC2_A5 & _LC3_A5 & !_LC5_A5
# _LC3_A5 & !_LC4_A5 & !_LC5_A5;
-- Node name is '|count_48:4|7448:3|:68' = '|count_48:4|7448:3|OB'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ002);
_EQ002 = !_LC2_A5 & !_LC5_A5
# _LC2_A5 & !_LC3_A5 & _LC5_A5
# !_LC3_A5 & !_LC4_A5
# !_LC4_A5 & !_LC5_A5;
-- Node name is '|count_48:4|7448:3|:70' = '|count_48:4|7448:3|OC'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ003);
_EQ003 = _LC2_A5 & !_LC3_A5
# _LC2_A5 & !_LC4_A5
# !_LC3_A5 & !_LC5_A5
# !_LC4_A5 & !_LC5_A5
# !_LC3_A5 & _LC4_A5;
-- Node name is '|count_48:4|7448:3|:67' = '|count_48:4|7448:3|OD'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ004);
_EQ004 = !_LC2_A5 & _LC5_A5
# _LC2_A5 & _LC4_A5 & !_LC5_A5
# !_LC4_A5 & _LC5_A5
# !_LC2_A5 & !_LC4_A5;
-- Node name is '|count_48:4|7448:3|:71' = '|count_48:4|7448:3|OE'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ005);
_EQ005 = !_LC2_A5 & !_LC4_A5
# !_LC2_A5 & _LC5_A5;
-- Node name is '|count_48:4|7448:3|:66' = '|count_48:4|7448:3|OF'
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = LCELL( _EQ006);
_EQ006 = !_LC2_A5 & !_LC5_A5
# _LC3_A5 & !_LC5_A5
# !_LC2_A5 & _LC4_A5
# _LC4_A5 & !_LC5_A5;
-- Node name is '|count_48:4|7448:3|:72' = '|count_48:4|7448:3|OG'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ007);
_EQ007 = !_LC2_A5 & _LC4_A5
# !_LC2_A5 & _LC5_A5
# !_LC2_A5 & _LC3_A5
# _LC4_A5 & !_LC5_A5
# _LC3_A5 & !_LC5_A5
# !_LC4_A5 & _LC5_A5
# _LC3_A5 & !_LC4_A5;
-- Node name is '|count_160:3|74160:3|:6' = '|count_160:3|74160:3|QA'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = DFFE( _EQ008, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ008 = !EN & _LC2_A5
# EN & !_LC2_A5;
-- Node name is '|count_160:3|74160:3|:7' = '|count_160:3|74160:3|QB'
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = DFFE( _EQ009, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ009 = _LC3_A5 & _LC5_A5
# !_LC2_A5 & _LC5_A5
# !EN & _LC5_A5
# EN & _LC2_A5 & !_LC3_A5 & !_LC5_A5;
-- Node name is '|count_160:3|74160:3|:8' = '|count_160:3|74160:3|QC'
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = DFFE( _EQ010, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ010 = !_LC2_A5 & _LC4_A5
# _LC4_A5 & !_LC5_A5
# !EN & _LC4_A5
# EN & _LC2_A5 & !_LC4_A5 & _LC5_A5;
-- Node name is '|count_160:3|74160:3|:9' = '|count_160:3|74160:3|QD'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = DFFE( _EQ011, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ011 = !_LC3_A5 & _LC8_A5
# EN & _LC2_A5 & _LC8_A5
# !_LC2_A5 & _LC3_A5 & !_LC8_A5
# !EN & _LC3_A5 & !_LC8_A5;
-- Node name is '|count_160:3|74160:3|:45' = '|count_160:3|74160:3|RCO'
-- Equation name is '_LC7_A5', type is buried
_LC7_A5 = LCELL( _EQ012);
_EQ012 = EN & _LC2_A5 & _LC3_A5;
-- Node name is '|count_160:3|74160:3|:46'
-- Equation name is '_LC8_A5', type is buried
_LC8_A5 = LCELL( _EQ013);
_EQ013 = EN & _LC2_A5 & _LC4_A5 & _LC5_A5;
Project Information g:\llp\count\count_10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,744K
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