h_adder.vhd

来自「本文件包是在MAX+plus II 软件环境下实现全加器的逻辑功能」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_ADDER IS
  PORT(A,B:IN STD_LOGIC;CO,SO:OUT STD_LOGIC);
END ENTITY H_ADDER;
ARCHITECTURE ART2 OF H_ADDER IS
 BEGIN
 SO<=A XOR B;
 CO<=A AND B;
END ARCHITECTURE ART2;