📄 main.mac
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;-------------------- ; macro.mac
INCDLN MACRO MEM
LDLN MEM
SED
CLC
ADC #01h
STLN MEM
CLD
ENDM
INCDHN MACRO MEM
LDHN MEM
SED
CLC
ADC #01h
STHN MEM
CLD
ENDM
RORLN MACRO mem
CLC
ROR mem-40h
ENDM
RORHN MACRO mem
CLC
ROR mem-20h
ENDM
CPLN MACRO mem
CMP mem-40h
ENDM
CPHN MACRO mem
CMP mem-20h
ENDM
INCD MACRO MEM
LDA MEM
SED
CLC
ADC #01h
STA MEM
CLD
ENDM
INCLN MACRO mem
INC mem-40h
ENDM
INCHN MACRO mem
INC mem-20h
ENDM
DECLN MACRO mem
DEC mem-40h
ENDM
DECHN MACRO mem
DEC mem-20h
ENDM
ADCHN MACRO mem
ADC mem-20h
ENDM
ADCLN MACRO mem
ADC mem-40h
ENDM
LDLN MACRO mem
LDA mem-40h
ENDM
LDHN MACRO mem
LDA mem-20h
ENDM
STLN MACRO mem
STA mem-40h
ENDM
STHN MACRO mem
STA mem-20h
ENDM
;------------------------------------
;------------------------------------
INCDA MACRO
SED
CLC
ADC #01h
CLD
ENDM
INCWD MACRO MEM
LDA MEM
SED
CLC
ADC #01h
STA MEM
LDA MEM+1
ADC #00h
STA MEM+1
CLD
ENDM
DECD MACRO MEM
LDA MEM
SED
SEC
SBC #01h
STA MEM
CLD
ENDM
DECXD MACRO MEM
LDA MEM,X
SED
SEC
SBC #01h
STA MEM,X
CLD
ENDM
DECDA MACRO
SED
SEC
SBC #01h
CLD
ENDM
DECWD MACRO MEM
LDA MEM
SED
SEC
SBC #01h
STA MEM
LDA MEM+1
SBC #00h
STA MEM+1
CLD
ENDM
ADCDi MACRO MEM,DD
SED
LDA MEM
CLC
ADC #DD
STA MEM
CLD
ENDM
ADCW MACRO MEM
CLC
ADC MEM
STA MEM
LDA #00h
ADC MEM+1
STA MEM+1
ENDM
ADCWDi MACRO MEM,DD
SED
LDA MEM
CLC
ADC #DD
STA MEM
LDA MEM+1
ADC #00h
STA MEM+1
CLD
ENDM
SBCDi MACRO MEM,DD
SED
LDA MEM
SEC
SBC #DD
STA MEM
CLD
ENDM
SBCWDi MACRO MEM,DD
SED
LDA MEM
SEC
SBC #DD
STA MEM
LDA MEM+1
SBC #00h
STA MEM+1
CLD
ENDM
ADCDm MACRO MEM,MEM2
SED
LDA MEM
CLC
ADC MEM2
STA MEM
CLD
ENDM
ADCWDm MACRO MEM,MEM2
SED
LDA MEM
CLC
ADC MEM2
STA MEM
LDA MEM+1
ADC MEM2+1
STA MEM+1
CLD
ENDM
SBCDm MACRO MEM,MEM2
SED
LDA MEM
SEC
SBC MEM2
STA MEM
CLD
ENDM
SBCWDm MACRO MEM,MEM2
SED
LDA MEM
SEC
SBC MEM2
STA MEM
LDA MEM+1
SBC MEM2+1
STA MEM+1
CLD
ENDM
;;//---------------------------------------------------------------
; angelo leung, 06-4-20 15:35
SBCWm MACRO MEM,MEM2
LDA MEM
SEC
SBC MEM2
STA MEM
LDA MEM+1
SBC MEM2+1
STA MEM+1
ENDM
ADDm MACRO MEM,MEM2
LDA MEM
CLC
ADC MEM2
STA MEM
LDA MEM+1
ADC MEM2+1
STA MEM+1
ENDM
;;//---------------------------------------------------------------
INCW MACRO MEM
INC MEM
BNE ?skip#
INC MEM+1
?skip#
ENDM
DECW MACRO MEM
PHA
LDA MEM
BNE ?skip#
DEC MEM+1
?skip#
DEC MEM
PLA
ENDM
HERE MACRO
?HHH#
WDT_RST
JMP ?HHH#
ENDM
SMBx MACRO MEM,BIT
LDA #(01h<<BIT)
ORA MEM
STA MEM
ENDM
RMBx MACRO MEM,BIT
LDA #(0FFh^(01h<<BIT))
AND MEM
STA MEM
ENDM
XMBx MACRO MEM,BIT
LDA #(01h<<BIT)
EOR MEM
STA MEM
ENDM
BR0 MACRO PARA,VAR,LABLE
BBR@<VAR> PARA,LABLE
ENDM
BR1 MACRO PARA,VAR,LABLE
BBS@<VAR> PARA,LABLE
ENDM
LBR0 MACRO PARA,VAR,LABLE
LDA #(01h<<VAR)
AND PARA
BEQ LABLE
ENDM
LBR1 MACRO PARA,VAR,LABLE
LDA #(01h<<VAR)
AND PARA
BNE LABLE
ENDM
LSETB MACRO PARA,VAR
LDA #(01h<<VAR)
ORA PARA
STA PARA
ENDM
LCLRB MACRO PARA,VAR
LDA #(0FFh^(01h<<VAR))
AND PARA
STA PARA
ENDM
;ZPFlagBN EQU Bytes
;ZPFlag DB ZPFlagBN
;fMelody EQU 0
JB MACRO var,label
if ZPFlagBN>(var/8)
BBS@<var.mod.8> ZPFlag+var/8,label
else
---FAIL--- Flag out of range
endif
ENDM
JNB MACRO var,label
if ZPFlagBN>(var/8)
BBR@<var.mod.8> ZPFlag+var/8,label
else
---FAIL--- Flag out of range
endif
ENDM
SETB MACRO var
if ZPFlagBN>(var/8)
SMB@<var.mod.8> ZPFlag+var/8
else
---FAIL--- Flag out of range
endif
ENDM
CLRB MACRO var
if ZPFlagBN>(var/8)
RMB@<var.mod.8> ZPFlag+var/8
else
---FAIL--- Flag out of range
endif
ENDM
EORB MACRO var
if ZPFlagBN>(var/8)
LDA #(01h<<(var.mod.8))
EOR ZPFlag+var/8
STA ZPFlag+var/8
else
---FAIL--- Flag out of range
endif
ENDM
xJB MACRO flag,bit,label
BBS@<bit> flag,label
ENDM
xJNB MACRO flag,bit,label
BBR@<bit> flag,label
ENDM
xSETB MACRO flag,bit
SMB@<bit> flag
ENDM
xCLRB MACRO flag,bit
RMB@<bit> flag
ENDM
xEORB MACRO flag,bit
LDA #(01h<<bit)
EOR flag
STA flag
ENDM
LCD32CxSx MACRO Cx,Sx
DB 32/8*Cx+Sx/8,(01h<<(Sx.mod.8))
ENDM
LCD32CxSS MACRO Cx,Sx,Sxx
DB 32/8*Cx+Sx/8,(01h<<(Sx.mod.8))+(01h<<(Sxx.mod.8))
ENDM
LCD32CxSb MACRO Cx,Sx
DB 32/8*Cx+Sx/8
ENDM
LCD40CxSx MACRO Cx,Sx
DB 40/8*Cx+Sx/8,(01h<<(Sx.mod.8))
ENDM
LCD48CxSx MACRO Cx,Sx
DB 48/8*Cx+Sx/8,(01h<<(Sx.mod.8))
ENDM
LCD40CxSS MACRO Cx,Sx,Sxx
DB 40/8*Cx+Sx/8,(01h<<(Sx.mod.8))+(01h<<(Sxx.mod.8))
ENDM
LCD40CxSb MACRO Cx,Sx
DB 40/8*Cx+Sx/8
ENDM
LCD40CxSxb MACRO Cx,Sx
DB 40/8*Cx+Sx/8,Sx.mod.8
ENDM
LCD40Cx MACRO Cx
DB 40/8*Cx
ENDM
LCD60CxSx MACRO Cx,Sx
DB 6*Cx+Sx/8,(01h<<(Sx.mod.8))
ENDM
SHIFT_LEFT_B MACRO memL,memH
LDLN memH
STHN memH
LDHN memL
STLN memH
ENDM
SHIFT_LEFT_B0 MACRO mem
LDLN mem
STHN mem
LDA #00h
STLN mem
ENDM
SHIFT_RIGHT_B MACRO memL,memH
LDHN memL
STLN memL
LDLN memH
STHN memL
ENDM
SHIFT_RIGHT_B0 MACRO mem
LDHN mem
STLN mem
LDA #00h
STHN mem
ENDM
SHIFT_RIGHT_B1 MACRO mem
LDHN mem
STLN mem
LDA #01h
STHN mem
ENDM
SHIFT_LEFT_B1 MACRO memL,memH
LDHN memL
STLN memH
ENDM
SHIFT_LEFT_X MACRO memL,memH
LDLN_X memH
STHN_X memH
LDHN_X memL
STLN_X memH
ENDM
SHIFT_LEFT_X0 MACRO mem
LDLN_X mem
STHN_X mem
LDA #00h
STLN_X mem
ENDM
SHIFT_RIGHT_X MACRO memL,memH
LDHN_X memL
STLN_X memL
LDLN_X memH
STHN_X memL
ENDM
SHIFT_RIGHT_X0 MACRO mem
LDHN_X mem
STLN_X mem
LDA #00h
STHN_X mem
ENDM
SHIFT_RIGHT_X1 MACRO mem
LDHN_X mem
STLN_X mem
LDA #01h
STHN_X mem
ENDM
SHIFT_LEFT_X1 MACRO memL,memH
LDHN_X memL
STLN_X memH
ENDM
;------------------ ; 2020.mac
;------------------------------------
TONE_VDD MACRO
RMB0 PADFUNC0
ENDM
TONE_TMR0 MACRO
SMB0 PADFUNC0
ENDM
;------------------------------------
EN_TMR0_IRQ MACRO
SMB1 IER
ENDM
EN_TMR1_IRQ MACRO
SMB2 IER
ENDM
EN_KEY_IRQ MACRO
SMB4 IER
ENDM
EN_LCD_IRQ MACRO
SMB6 IER
ENDM
DIS_TMR0_IRQ MACRO
RMB1 IER
ENDM
DIS_TMR1_IRQ MACRO
RMB2 IER
ENDM
DIS_KEY_IRQ MACRO
RMB4 IER
ENDM
DIS_LCD_IRQ MACRO
RMB6 IER
ENDM
;------------------------------------
IF_DIV_IRQ_FLAG MACRO LAB1
BBS0 IFR,LAB1
ENDM
IF_NOT_DIV_IRQ_FLAG MACRO LAB1
BBR0 IFR,LAB1
ENDM
IF_TMR0_IRQ_FLAG MACRO LAB1
BBS1 IFR,LAB1
ENDM
IF_NOT_TMR0_IRQ_FLAG MACRO LAB1
BBR1 IFR,LAB1
ENDM
IF_TMR1_IRQ_FLAG MACRO LAB1
BBS2 IFR,LAB1
ENDM
IF_KEY_IRQ_FLAG MACRO LAB1
BBS4 IFR,LAB1
ENDM
IF_LCD_IRQ_FLAG MACRO LAB1
BBS6 IFR,LAB1
ENDM
IF_NOT_LCD_IRQ_FLAG MACRO LAB1
BBR6 IFR,LAB1
ENDM
;------------------------------------
CLR_DIV_IRQ_FLAG MACRO
RMB0 IFR
ENDM
CLR_TMR0_IRQ_FLAG MACRO
RMB1 IFR
ENDM
CLR_TMR1_IRQ_FLAG MACRO
RMB2 IFR
ENDM
CLR_KEY_IRQ_FLAG MACRO
RMB4 IFR
ENDM
CLR_LCD_IRQ_FLAG MACRO
RMB6 IFR
ENDM
;------------------------------------
Fext_OFF MACRO
RMB1 SYSCLK
ENDM
Fext_ON MACRO
SMB1 SYSCLK
ENDM
Fsub_Fext MACRO
Fext_ON
ENDM
Fsub_32KCLK MACRO
Fext_OFF
ENDM
Fosc_OFF MACRO
RMB2 SYSCLK
ENDM
Fosc_ON MACRO
SMB2 SYSCLK
ENDM
Fcpu_Fext MACRO
SMB7 SYSCLK
RMB2 SYSCLK
ENDM
Fcpu_Fsys MACRO
SMB2 SYSCLK
RMB7 SYSCLK
ENDM
TMR1_S_Fsub MACRO
RMB2 TMCLK
ENDM
TMR1_S_Fosc MACRO
SMB2 TMCLK
ENDM
;------------------------------------
TMR0_ON MACRO
SMB0 TMRCTL
ENDM
TMR0_OFF MACRO
RMB0 TMRCTL
ENDM
TMR1_ON MACRO
SMB1 TMRCTL
ENDM
TMR1_OFF MACRO
RMB1 TMRCTL
ENDM
LCD_ON MACRO
SMB4 TMRCTL
ENDM
LCD_OFF MACRO
RMB4 TMRCTL
ENDM
PWM_ON MACRO
SMB7 TMRCTL
ENDM
PWM_OFF MACRO
RMB7 TMRCTL
ENDM
IF_PWM_ON MACRO LAB
BBS7 TMRCTL,LAB
ENDM
IF_PWM_OFF MACRO LAB
BBR7 TMRCTL,LAB
ENDM
;------------------------------------
3Bias MACRO
SMB6 LCD_CTL
ENDM
4Bias MACRO
RMB6 LCD_CTL
ENDM
;---------------------------
;---------------------------
;-------------------------- ; new.mac
CAJE MACRO mem1,mem2,LABEL
LDA mem1
CMP mem2
BNE $+5
JMP LABEL
ENDM
;------------------------------------
BBR MACRO MEM,BIT,LABEL
LDA #(01h<<BIT)
AND MEM
BNE $+5
JMP LABEL
ENDM
;------------------------------------
CAJNE MACRO mem1,mem2,LABEL
LDA mem1
CMP mem2
BEQ $+5
JMP LABEL
ENDM
;------------------------------------
CAJHE MACRO mem1,mem2,LABEL
LDA mem1
CPHN mem2
BNE $+5
JMP LABEL
ENDM
;------------------------------------
CAJLE MACRO mem1,mem2,LABEL
LDA mem1
CPLN mem2
BNE $+5
JMP LABEL
ENDM
;------------------------------------
;;2004-12-23
_AToSP MACRO ; set SP from A reg
TAX ; rv9⌨️ 快捷键说明
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