fifo.v

来自「采用Verilog语言描述的FIFO和双端口RAM源代码。」· Verilog 代码 · 共 41 行

/*2007-9-29 jhw*/
module FIFO(datain,wren,rden,dataout,clk,full,empty);
input [7:0] datain;
input wren,rden,clk;
output [7:0] dataout;
output full,empty;

reg [7:0] datain_buffer,dataout;
reg full,empty;
reg [7:0] mem[0:31];
reg [4:0] current_addr;
reg [5:0] count;
always@(negedge clk)
	case({wren,rden})
	2'b10:
		begin
			mem[current_addr]=datain_buffer;
			current_addr=current_addr+1;
			count=count+1;
		end
	2'b01:
		begin
			current_addr=current_addr-1;
			dataout=mem[current_addr];
			count=count-1;
		end
	default:;
	endcase

always@(posedge clk)
	if(wren)datain_buffer=datain;
	
always@(posedge clk)
	if(count==0)empty=1'b1;
	else empty=1'b0;
	
always@(posedge clk)
	if(count==32)full=1'b1;
	else full=1'b0;
endmodule