tc1_1.sym

arm的功能测试模块

00000000 W __heap_end
00000000 a __tmp_reg__
00000000 W __vector_default
00000000 T __vectors
00000001 a __zero_reg__
0000003d a __SP_L__
0000003e a __SP_H__
0000003f a __SREG__
00000054 T __ctors_end
00000054 T __ctors_start
00000054 T __dtors_end
00000054 T __dtors_start
00000054 W __init
00000060 T __do_copy_data
0000006c t .do_copy_data_loop
00000070 t .do_copy_data_start
00000076 T __do_clear_bss
0000007e t .do_clear_bss_loop
00000080 t .do_clear_bss_start
0000008a T __bad_interrupt
0000008a W __vector_1
0000008a W __vector_10
0000008a W __vector_11
0000008a W __vector_12
0000008a W __vector_13
0000008a W __vector_14
0000008a W __vector_15
0000008a W __vector_16
0000008a W __vector_17
0000008a W __vector_18
0000008a W __vector_19
0000008a W __vector_2
0000008a W __vector_20
0000008a W __vector_3
0000008a W __vector_4
0000008a W __vector_6
0000008a W __vector_7
0000008a W __vector_8
0000008a W __vector_9
0000008e T b16td5
00000158 T smiao
000001ac T t2pwm2
000001d0 T init_timer1
000001f4 T __vector_5
0000025c T main
00000338 A __data_load_start
00000338 T _etext
00000348 A __data_load_end
0000045f W __stack
00800060 D __data_start
00800060 D num_g
00800061 D num_sh
00800062 D num_b
00800063 D num_q
00800064 D num_w
00800070 B __bss_start
00800070 D __data_end
00800070 D _edata
00800070 B i_q
00800071 B i_sh
00800072 B temp2
00800074 B i_g
00800075 B temp1
00800077 B num
00800078 B i_w
00800079 B i_b
0080007a B __bss_end
0080007a ? _end
00810000 ? __eeprom_end