📄 rtl8139.h
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#include <tmlib/tmtypes.h>
#include <tm1/mmio.h>
#include <tm1/tmProcessor.h>
#include <ops/custom_defs.h>
#include <tm1/tmInterrupts.h>
#include <tmlib/dprintf.h>
#include <tm1/mmio.h>
#include <tm1/tmIntPins.h>
#include "bsp.h"
#include <pna.h>
#include <psos.h>
#include <pna_mib.h>
#include <bspfuncs.h>
/*
#define USHORT unsigned short
#define BYTE unsigned char
#define WORD unsigned short
#define DWORD unsigned long
#define USHORT unsigned short
#define ULONG unsigned long
*/
#include "common.h"
#define USHORT unsigned short
//#define BYTE unsigned char
#define WORD unsigned short
#define DWORD unsigned long
#define USHORT unsigned short
#define ULONG unsigned long
#define V_LAN intINT_0
#define TRUE 1
#define FALSE 0
#define DE_CPU 0x10000//0x8000000
#define EN_CPU 0x1000
#define PRO_CPU 0x2000
#define RTK8139 0x20000//0x10000000
#define REALTEK_8139_ID 0x8129
//---------------------------------------------------------------------
// Symbol Definitions
//---------------------------------------------------------------------
#define CFID 0x00
#define CFCS 0x04
#define CF_CMD 0x04
#define CF_STATUS 0x06
#define CFRV 0x08
#define CFLT 0x0C
#define CF_LINE_SZ 0x0C
#define CF_LATENCY 0x0D
#define CBIO 0x10
#define CBMA 0x14
#define CCIS 0x28
#define CSID 0x2c
#define CBER 0x30
#define CCAP 0x34
#define CFIT 0x3C
#define CFDD 0x40
#define CF_DRIVER 0x41
#define CWUA0 0x44
#define CWUA1 0x48
#define SOP0 0x4c
#define SOP1 0x50
#define CWUC 0x54
#define CCID 0xDC
#define CPMC 0xE0
//---------------------------------------------------------------------
// Receive status register
//---------------------------------------------------------------------
#define LAN_RCVD_MAR 1 << 15
#define LAN_RCVD_PAM 1 << 14
#define LAN_RCVD_BAR 1 << 13
#define LAN_RCVD_ISE 1 << 5
#define LAN_RCVD_RUNT 1 << 4
#define LAN_RCVD_LONG 1 << 3
#define LAN_RCVD_CRC 1 << 2
#define LAN_RCVD_FAE 1 << 1
#define LAN_RCVD_ROK 1
//---------------------------------------------------------------------
// Device Status Register
//---------------------------------------------------------------------
#define LAN_DS_PER 0x8000 //Parity error detected
#define LAN_DS_SERR 0x4000 //SERR# Status
#define LAN_DS_MA 0x2000 //Master-Abort Status
#define LAN_DS_RTA 0x1000 //Received Target-Abort
#define LAN_DS_DEVT 0x0200 //Device Select Timing
#define LAN_DS_DPAR 0x0100 //Data Parity Report
#define LAN_DS_FB2B 0x0080 //Fast Back to Back capable
#define LAN_DS_NEWC 0x0010 //New Capabilities
//---------------------------------------------------------------------
// PCI address of the chip's Control and Status Registers
//---------------------------------------------------------------------
#define LAN_PCI_IO_BASE 0xd0000000// 0xe8000000
//---------------------------------------------------------------------
// 8139 Control and Status registers
//---------------------------------------------------------------------
#define IDR0 (LAN_PCI_IO_BASE + 0x00) //ID Register 0
#define IDR1 (LAN_PCI_IO_BASE + 0x01) //ID Register 1
#define IDR2 (LAN_PCI_IO_BASE + 0x02) //ID Register 2
#define IDR3 (LAN_PCI_IO_BASE + 0x03) //ID Register 3
#define IDR4 (LAN_PCI_IO_BASE + 0x04) //ID Register 4
#define IDR5 (LAN_PCI_IO_BASE + 0x05) //ID Register 5
#define MAR0 (LAN_PCI_IO_BASE + 0x08) //Multicast Register 0,
#define MAR1 (LAN_PCI_IO_BASE + 0x09) //Multicast Register 1
#define MAR2 (LAN_PCI_IO_BASE + 0x0a) //Multicast Register 2
#define MAR3 (LAN_PCI_IO_BASE + 0x0b) //Multicast Register 3
#define MAR4 (LAN_PCI_IO_BASE + 0x0c) //Multicast Register 4
#define MAR5 (LAN_PCI_IO_BASE + 0x0d) //Multicast Register 5
#define MAR6 (LAN_PCI_IO_BASE + 0x0e) //Multicast Register 6
#define MAR7 (LAN_PCI_IO_BASE + 0x0f) //Multicast Register 7
#define TSD0 (LAN_PCI_IO_BASE + 0x10) //Transmit Status of Descriptor 0
#define TSD1 (LAN_PCI_IO_BASE + 0x14) //Transmit Status of Descriptor 1
#define TSD2 (LAN_PCI_IO_BASE + 0x18) //Transmit Status of Descriptor 2
#define TSD3 (LAN_PCI_IO_BASE + 0x1c) //Transmit Status of Descriptor 3
#define TSAD0 (LAN_PCI_IO_BASE + 0x20) //Transmit Start Address of Descriptor0
#define TSAD1 (LAN_PCI_IO_BASE + 0x24) //Transmit Start Address of Descriptor1
#define TSAD2 (LAN_PCI_IO_BASE + 0x28) //Transmit Start Address of Descriptor2
#define TSAD3 (LAN_PCI_IO_BASE + 0x2c) //Transmit Start Address of Descriptor3
#define RBSTART (LAN_PCI_IO_BASE + 0x30) //Receive (Rx) Buffer Start Address
#define ERBCR (LAN_PCI_IO_BASE + 0x34) //Early Receive (Rx) Byte Count Register
#define ERSR (LAN_PCI_IO_BASE + 0x36) //Early Rx Status Register
#define CR (LAN_PCI_IO_BASE + 0x37) //Command Register
#define CAPR (LAN_PCI_IO_BASE + 0x38) //Current Address of Packet Read
#define CBR (LAN_PCI_IO_BASE + 0x3a) //Current Buffer Address
#define IMR (LAN_PCI_IO_BASE + 0x3c) //Interrupt Mask Register
#define ISR (LAN_PCI_IO_BASE + 0x3e) //Interrupt Status Register
#define TCR (LAN_PCI_IO_BASE + 0x40) //Transmit (Tx) Configuration Register
#define RCR (LAN_PCI_IO_BASE + 0x44) //Receive (Rx) Configuration Register
#define TCTR (LAN_PCI_IO_BASE + 0x48) //Timer CounT Register
#define MPC (LAN_PCI_IO_BASE + 0x4c) //Missed Packet Counter
#define CR9346 (LAN_PCI_IO_BASE + 0x50) //93C46 (93C56) Command Register
#define CONFIG0 (LAN_PCI_IO_BASE + 0x51) //Configuration Register 0
#define CONFIG1 (LAN_PCI_IO_BASE + 0x52) //Configuration Register 1
#define TIMERINT (LAN_PCI_IO_BASE + 0x54) //Timer Interrupt Register
#define MSR (LAN_PCI_IO_BASE + 0x58) //Media Status Register
#define CONFIG3 (LAN_PCI_IO_BASE + 0x59) //Configuration register 3
#define CONFIG4 (LAN_PCI_IO_BASE + 0x5a) //Configuration register 4
#define MULINT (LAN_PCI_IO_BASE + 0x5c) //Multiple Interrupt Select
#define RERID (LAN_PCI_IO_BASE + 0x5e) //PCI Revision ID = 10h.
#define TSAD (LAN_PCI_IO_BASE + 0x60) //Transmit Status of All Descriptors
#define BMCR (LAN_PCI_IO_BASE + 0x62) //Basic Mode Control Register
#define BMSR (LAN_PCI_IO_BASE + 0x64) //Basic Mode Status Register
#define ANAR (LAN_PCI_IO_BASE + 0x66) //Auto-Negotiation Advertisement Register
#define ANLPAR (LAN_PCI_IO_BASE + 0x68) //Auto-Negotiation Link Partner Register
#define ANER (LAN_PCI_IO_BASE + 0x6a) //Auto-Negotiation Expansion Register
#define DIS (LAN_PCI_IO_BASE + 0x6c) //Disconnect Counter
#define FCSC (LAN_PCI_IO_BASE + 0x6e) //False Carrier Sense Counter
#define NWAYTR (LAN_PCI_IO_BASE + 0x70) //N-way Test Register
#define CSCR (LAN_PCI_IO_BASE + 0x74) //CS Configuration Register
#define PHY1_PARM (LAN_PCI_IO_BASE + 0x78) //PHY parameter 1
#define TW_PARM (LAN_PCI_IO_BASE + 0x7c) //Twister parameter
#define PHY2_PARM (LAN_PCI_IO_BASE + 0x80) //PHY parameter 2
#define CRC0 (LAN_PCI_IO_BASE + 0x84) //Power Management CRC register0 for wakeup frame0
#define WAKEUP0 (LAN_PCI_IO_BASE + 0x8c) //Power Management wakeup frame0 (64bit)
#define LSBCRC0 (LAN_PCI_IO_BASE + 0xcc) //LSB of the mask byte of wakeup frame0 within offset 12 to 75
#define CONFIG5 (LAN_PCI_IO_BASE + 0xd8) //Configuration register 5
void PciWriteConfig32(ULONG pci_device, ULONG addr, ULONG value);
void PciWriteConfig16(ULONG pci_device, ULONG addr, USHORT value);
void PciWriteConfig8(ULONG pci_device, ULONG addr, UCHAR value);
ULONG PciReadConfig32(ULONG pci_device, ULONG addr);
USHORT PciReadConfig16(ULONG pci_device, ULONG addr);
UCHAR PciReadConfig8(ULONG pci_device, ULONG addr);
#define PciWrCfg32(addr, value) PciWriteConfig32(RTK8139, addr, value)
#define PciWrCfg16(addr, value) PciWriteConfig16(RTK8139, addr, value)
#define PciWrCfg8(addr, value) PciWriteConfig8(RTK8139, addr, value)
#define PciRdCfg32(addr) PciReadConfig32(RTK8139, addr)
#define PciRdCfg16(addr) PciReadConfig16(RTK8139, addr)
#define PciRdCfg8(addr) PciReadConfig8(RTK8139, addr)
ULONG IoReadReg32(ULONG addr);
USHORT IoReadReg16(ULONG addr);
UCHAR IoReadReg8(ULONG addr);
void IoWriteReg32(ULONG addr, ULONG value);
void IoWriteReg16(ULONG addr, USHORT value);
void IoWriteReg8(ULONG addr, UCHAR value);
void TestLoopBack();
#ifdef NO_DP8139
#define DP8139
#define DP8139size(size)
#else
#define DP8139 _dp
#define DP8139size(size) _dp_start(size, Null)
#endif
//zzm [2005-11-9]
//#define DEFAULT_LAN_IP 0x0A6E72F0 //10.110.114.240
//#define DEFAULT_GATEWAY 0x0A6E72FE //10.110.114.254
#define DEFAULT_LAN_IP 0xC0A8000F //192.168.0.15
#define DEFAULT_SUBNETMASK 0xFFFFFF00 //255.255.255.0
#define DEFAULT_GATEWAY 0xC0A80001 //192.168.0.1
#define DEFAULT_GATE_LANIP 0XC0A80000A //梯口默认IP地址192.168.0.10
#define DEFAULT_GATE_SUBNETMASK 0XFFFFFF00 //梯口默认掩码
#define DEFAULT_GATE_GATEWAY 0XC0A80001 //梯口默认网关
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