mv_gen_reg.h

omap osk环境下的bootloader,包含完整的uboot源代码

/****************************************/
/*	    Snoop Control			*/
/****************************************/

/*#define SNOOP_BASE_ADDRESS_0				      0x380
#define SNOOP_TOP_ADDRESS_0				    0x388
#define SNOOP_BASE_ADDRESS_1				    0x390
#define SNOOP_TOP_ADDRESS_1				    0x398
#define SNOOP_BASE_ADDRESS_2				    0x3a0
#define SNOOP_TOP_ADDRESS_2				    0x3a8
#define SNOOP_BASE_ADDRESS_3				    0x3b0
#define SNOOP_TOP_ADDRESS_3				    0x3b8
*/

/****************************************/
/*  Integrated SRAM Registers		*/
/****************************************/

#define SRAM_CONFIG						0x380
#define SRAM_TEST_MODE						0x3F4
#define SRAM_ERROR_CAUSE					0x388
#define SRAM_ERROR_ADDR						0x390
#define SRAM_ERROR_ADDR_HIGH					0x3F8
#define SRAM_ERROR_DATA_LOW					0x398
#define SRAM_ERROR_DATA_HIGH					0x3a0
#define SRAM_ERROR_DATA_PARITY					0x3a8

/****************************************/
/*	    CPU Error Report			*/
/****************************************/

#define CPU_ERROR_ADDRESS_LOW		0x070
#define CPU_ERROR_ADDRESS_HIGH		0x078
#define CPU_ERROR_DATA_LOW					0x128
#define CPU_ERROR_DATA_HIGH					0x130
#define CPU_ERROR_PARITY					0x138
#define CPU_ERROR_CAUSE						0x140
#define CPU_ERROR_MASK						0x148

#define CPU_ERROR_ADDR_LOW					CPU_ERROR_ADDRESS_LOW  /* 0x0701 */
#define CPU_ERROR_ADDR_HIGH					CPU_ERROR_ADDRESS_HIGH	/* 0x0781 */

/****************************************/
/*	    Pslave Debug			*/
/*	CPU Interface Debug Registers	*/
/****************************************/

#define X_0_ADDRESS						0x360
#define X_0_COMMAND_ID						0x368
#define X_1_ADDRESS						0x370
#define X_1_COMMAND_ID						0x378
 /*#define WRITE_DATA_LOW					0x3c01 */
 /*#define WRITE_DATA_HIGH					0x3c81 */
 /*#define WRITE_BYTE_ENABLE					0x3e01 */
 /*#define READ_DATA_LOW					0x3d01 */
 /*#define READ_DATA_HIGH					0x3d81 */
 /*#define READ_ID						0x3e81 */

#define PUNIT_SLAVE_DEBUG_LOW					X_0_ADDRESS  /* 0x3601 */
#define PUNIT_SLAVE_DEBUG_HIGH					X_0_COMMAND_ID	/* 0x3681 */
#define PUNIT_MASTER_DEBUG_LOW					X_1_ADDRESS  /* 0x3701 */
#define PUNIT_MASTER_DEBUG_HIGH				   X_1_COMMAND_ID  /* 0x3781 */
#define PUNIT_MMASK						0x3e4


/****************************************/
/* SDRAM and Device Address Space		*/
/****************************************/

/****************************************/
/* SDRAM Configuration			*/
/****************************************/
#define SDRAM_CONFIG						0x1400	/* MV64260 0x448 some changes*/
#define D_UNIT_CONTROL_LOW					0x1404	/* NEW in MV64360 and MV64460 */
#define D_UNIT_CONTROL_HIGH					0x1424	/* NEW in MV64360 and MV64460 */
#define SDRAM_TIMING_CONTROL_LOW			0x1408	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
#define SDRAM_TIMING_CONTROL_HIGH			0x140c	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
#define SDRAM_ADDR_CONTROL				    0x1410	/* MV64260 0x47c some changes*/
#define SDRAM_OPEN_PAGES_CONTROL			0x1414	/* NEW in MV64360 and MV64460 */
#define SDRAM_OPERATION						0x1418	/* MV64260 0x474 some changes*/
#define SDRAM_MODE						0x141c	/* NEW in MV64360 and MV64460 */
#define EXTENDED_DRAM_MODE					0x1420	/* NEW in MV64360 and MV64460 */
#define SDRAM_CROSS_BAR_CONTROL_LOW			0x1430	/* MV64260 0x4a8 NO changes*/
#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x1434	/* MV64260 0x4ac NO changes*/
#define SDRAM_CROSS_BAR_TIMEOUT				0x1438	/* MV64260 0x4b0 NO changes*/
#define SDRAM_ADDR_CTRL_PADS_CALIBRATION	0x14c0	/* what is this ??? */
#define SDRAM_DATA_PADS_CALIBRATION			0x14c4	/* what is this ??? */
/****************************************/
/* SDRAM Configuration MV64260			*/
/****************************************/
 /*#define SDRAM_CONFIGURATION			0x4481 */
 /*#define SDRAM_OPERATION_MODE			0x4741 */
 /*#define SDRAM_ADDRESS_DECODE		0x47c1 */
 /*#define SDRAM_UMA_CONTROL			0x4a4	eliminated in MV64360 and MV64460 */
 /*#define SDRAM_CROSS_BAR_CONTROL_LOW	0x4a81 */
 /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */
 /*#define SDRAM_CROSS_BAR_TIMEOUT		0x4b01 */
 /*#define SDRAM_TIMING				0x4b41 */


/****************************************/
/* SDRAM Error Report			*/
/****************************************/
#define SDRAM_ERROR_DATA_LOW				0x1444	/* MV64260 0x484 NO changes*/
#define SDRAM_ERROR_DATA_HIGH					0x1440	/* MV64260 0x480 NO changes*/
#define SDRAM_ERROR_ADDR					0x1450	/* MV64260 0x490 NO changes*/
#define SDRAM_RECEIVED_ECC					0x1448	/* MV64260 0x488 NO changes*/
#define SDRAM_CALCULATED_ECC					0x144c	/* MV64260 0x48c NO changes*/
#define SDRAM_ECC_CONTROL					0x1454	/* MV64260 0x494 NO changes*/
#define SDRAM_ECC_ERROR_COUNTER				0x1458	/* MV64260 0x498 NO changes*/
#define SDRAM_MMASK					0x1B40	/* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/
/****************************************/
/* SDRAM Error Report MV64260			*/
/****************************************/
 /*#define SDRAM_ERROR_DATA_LOW					0x4841 */
 /*#define SDRAM_ERROR_DATA_HIGH				0x4801 */
 /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS		0x4901 */
 /*#define SDRAM_RECEIVED_ECC				       0x4881 */
 /*#define SDRAM_CALCULATED_ECC					0x48c1 */
 /*#define SDRAM_ECC_CONTROL					0x4941 */
 /*#define SDRAM_ECC_ERROR_COUNTER			0x4981 */

/******************************************/
/*  Controlled Delay Line (CDL) Registers */
/******************************************/
#define DFCDL_CONFIG0						0x1480
#define DFCDL_CONFIG1						0x1484
#define DLL_WRITE						0x1488
#define DLL_READ						0x148c
#define SRAM_ADDR						0x1490
#define SRAM_DATA0						0x1494
#define SRAM_DATA1						0x1498
#define SRAM_DATA2						0x149c
#define DFCL_PROBE						0x14a0


/****************************************/
/* SDRAM Parameters only in MV64260			*/
/****************************************/

 /*#define SDRAM_BANK0PARAMETERS				0x44C	eliminated in MV64360 and MV64460 */
 /*#define SDRAM_BANK1PARAMETERS				0x450	eliminated in MV64360 and MV64460 */
 /*#define SDRAM_BANK2PARAMETERS				0x454	eliminated in MV64360 and MV64460 */
 /*#define SDRAM_BANK3PARAMETERS				0x458	eliminated in MV64360 and MV64460 */

/******************************************/
/*   Debug Registers			  */
/******************************************/

#define DUNIT_DEBUG_LOW						0x1460
#define DUNIT_DEBUG_HIGH					0x1464
#define DUNIT_MMASK						0x1b40

/****************************************/
/* SDunit Debug (for internal use)	*/
/****************************************/

#define X0_ADDRESS					    0x500
#define X0_COMMAND_AND_ID				    0x504
#define X0_WRITE_DATA_LOW				    0x508
#define X0_WRITE_DATA_HIGH				    0x50c
#define X0_WRITE_BYTE_ENABLE				    0x518
#define X0_READ_DATA_LOW				    0x510
#define X0_READ_DATA_HIGH				    0x514
#define X0_READ_ID					    0x51c
#define X1_ADDRESS					    0x520
#define X1_COMMAND_AND_ID				    0x524
#define X1_WRITE_DATA_LOW				    0x528
#define X1_WRITE_DATA_HIGH				    0x52c
#define X1_WRITE_BYTE_ENABLE				    0x538
#define X1_READ_DATA_LOW				    0x530
#define X1_READ_DATA_HIGH				    0x534
#define X1_READ_ID					    0x53c
#define X0_SNOOP_ADDRESS				    0x540
#define X0_SNOOP_COMMAND				    0x544
#define X1_SNOOP_ADDRESS				    0x548
#define X1_SNOOP_COMMAND				    0x54c

/****************************************/
/* Device Parameters					*/
/****************************************/

#define DEVICE_BANK0PARAMETERS				0x45c
#define DEVICE_BANK1PARAMETERS				0x460
#define DEVICE_BANK2PARAMETERS				0x464
#define DEVICE_BANK3PARAMETERS				0x468
#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
#define DEVICE_CONTROL							0x4c0
#define DEVICE_CROSS_BAR_CONTROL_LOW				0x4c8
#define DEVICE_CROSS_BAR_CONTROL_HIGH				0x4cc
#define DEVICE_CROSS_BAR_TIMEOUT				0x4c4

/****************************************/
/* Device Parameters					*/
/****************************************/

#define DEVICE_BANK0_PARAMETERS			DEVICE_BANK0PARAMETERS	/* 0x45c1 */
#define DEVICE_BANK1_PARAMETERS			DEVICE_BANK1PARAMETERS	/* 0x4601 */
#define DEVICE_BANK2_PARAMETERS			DEVICE_BANK2PARAMETERS	/* 0x4641 */
#define DEVICE_BANK3_PARAMETERS			DEVICE_BANK3PARAMETERS	/* 0x4681 */
/*#define DEVICE_BOOT_BANK_PARAMETERS			 0x46c1 */
#define DEVICE_INTERFACE_CONTROL				DEVICE_CONTROL	/* 0x4c01 */
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		DEVICE_CROSS_BAR_CONTROL_LOW  /* 0x4c81 */
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		DEVICE_CROSS_BAR_CONTROL_HIGH  /* 0x4cc1 */
#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT			DEVICE_CROSS_BAR_TIMEOUT  /* 0x4c41 */


/****************************************/
/* Device Interrupt					*/
/****************************************/

#define DEVICE_INTERRUPT_CAUSE						0x4d0
#define DEVICE_INTERRUPT_MASK						0x4d4
#define DEVICE_ERROR_ADDRESS						0x4d8
 /*#define DEVICE_INTERRUPT_CAUSE				0x4d01 */
 /*#define DEVICE_INTERRUPT_MASK				0x4d41 */
#define DEVICE_ERROR_ADDR				DEVICE_ERROR_ADDRESS  /*0x4d81 */
#define DEVICE_ERROR_DATA				0x4dc
#define DEVICE_ERROR_PARITY					0x4e0

/****************************************/
/* Device debug registers			*/
/****************************************/

#define DEVICE_DEBUG_LOW					0x4e4
#define DEVICE_DEBUG_HIGH				0x4e8
#define RUNIT_MMASK							0x4f0

/****************************************/
/* DMA Record							*/
/****************************************/

 /*#define CHANNEL4_DMA_BYTE_COUNT			0x9001 */
 /*#define CHANNEL5_DMA_BYTE_COUNT			0x9041 */
 /*#define CHANNEL6_DMA_BYTE_COUNT			0x9081 */
 /*#define CHANNEL7_DMA_BYTE_COUNT			0x90C1 */
 /*#define CHANNEL4_DMA_SOURCE_ADDRESS		0x9101 */
 /*#define CHANNEL5_DMA_SOURCE_ADDRESS		0x9141 */
 /*#define CHANNEL6_DMA_SOURCE_ADDRESS		0x9181 */
 /*#define CHANNEL7_DMA_SOURCE_ADDRESS		0x91C1 */
 /*#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x9201 */
 /*#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x9241 */
 /*#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x9281 */
 /*#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C1 */
 /*#define CHANNEL4NEXT_RECORD_POINTER			0x9301 */
 /*#define CHANNEL5NEXT_RECORD_POINTER			0x9341 */
 /*#define CHANNEL6NEXT_RECORD_POINTER			0x9381 */
 /*#define CHANNEL7NEXT_RECORD_POINTER			0x93C1 */
 /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x9701 */
 /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x9741 */
 /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x9781 */
 /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C1 */
 /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8901 */
 /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8941 */
 /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8981 */
 /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x89c1 */
 /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9901 */
 /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9941 */
 /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9981 */
 /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x99c1 */
 /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a01 */
 /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a41 */
 /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a81 */
 /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8ac1 */
 /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a01 */
 /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a41 */
 /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a81 */
 /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9ac1 */
 /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b01 */
 /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b41 */
 /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b81 */
 /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc1 */
 /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b01 */
 /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b41 */
 /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b81 */
 /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc1 */

/****************************************/
/* DMA Channel Control					*/
/****************************************/

#define CHANNEL0CONTROL					0x840
#define CHANNEL0CONTROL_HIGH				0x880
#define CHANNEL1CONTROL					0x844
#define CHANNEL1CONTROL_HIGH				0x884
#define CHANNEL2CONTROL					0x848
#define CHANNEL2CONTROL_HIGH				0x888
#define CHANNEL3CONTROL					0x84C
#define CHANNEL3CONTROL_HIGH				0x88C

#define DMA_CHANNEL0_CONTROL				CHANNEL0CONTROL	 /*0x8401 */
#define DMA_CHANNEL0_CONTROL_HIGH			CHANNEL0CONTROL_HIGH  /*0x8801 */
#define DMA_CHANNEL1_CONTROL				CHANNEL1CONTROL	 /* 0x8441 */
#define DMA_CHANNEL1_CONTROL_HIGH			CHANNEL1CONTROL_HIGH  /*0x8841 */
#define DMA_CHANNEL2_CONTROL				CHANNEL2CONTROL	 /*0x8481 */
#define DMA_CHANNEL2_CONTROL_HIGH			CHANNEL2CONTROL_HIGH  /*0x8881 */