dw8051_timer.v

DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.

    begin 
      t0_l0    <= 0;
      t1_l0    <= 0;
      t0_l1    <= 0;
      t1_l1    <= 0;
      t0_l2    <= 0;
      t1_l2    <= 0;
      gate0    <= 0;
      gate1    <= 0;
      int0_l_n <= 0;
      int1_l_n <= 0;
    end
    else
    begin
      t0_l0    <= t0;		// Stage 0 synchronizer
      t1_l0    <= t1;		// works unconditionally for all clock phases
      int0_l_n <= int0_n;
      int1_l_n <= int1_n;
      if (cycle == `c1)
      begin 
        t0_l1 <= t0_l0;		// Stage 1 and Stage 2 synchronizers
        t1_l1 <= t1_l0;		// are enabled only at the end of
        t0_l2 <= t0_l1;		// clock phase C1
        t1_l2 <= t1_l1;
        gate0 <= int0_l_n;
        gate1 <= int1_l_n;
      end 
    end 
  end  //inp_latch_process


  // detect high to low transition on t0,t1 inputs
  assign t0_event = (cycle == `c2) ? (t0_l2 & ~t0_l1) : 0;
  assign t1_event = (cycle == `c2) ? (t1_l2 & ~t1_l1) : 0;

// Mode 0 definitions
  assign mode0 = ((m00 == 0) & (m01 == 0)) ? `t0_13_bit      :
                 ((m00 == 1) & (m01 == 0)) ? `t0_16_bit      :
                 ((m00 == 0) & (m01 == 1)) ? `t0_auto_reload :
                                             `t0_2x8_bit;
// Mode 1 definitions
  assign mode1 = ((m10 == 0) & (m11 == 0)) ? `t1_13_bit      :
                 ((m10 == 1) & (m11 == 0)) ? `t1_16_bit      :
                 ((m10 == 0) & (m11 == 1)) ? `t1_auto_reload :
                                             `t1_off;
  // Definining the write-enables for TH0/1 and TL0/1
  assign  tl0_wr = sfr_wr & tl0_cs;
  assign  th0_wr = sfr_wr & th0_cs;
  assign  tl1_wr = sfr_wr & tl1_cs;
  assign  th1_wr = sfr_wr & th1_cs;

// Parallel load control for TL0
  assign ld_tl0_n = (tl0_wr == 1)              ? 0         :
                    (mode0 == `t0_auto_reload) ? ~tl0_sat8 :
                                                 1;
// Parallel load control for TH0
  assign ld_th0_n = (th0_wr == 1) ? 0 : 1;

// Parallel load DATA for TL0
  assign tl0_in  = (tl0_wr == 1) ? timer_data_in : th0_reg;

// Parallel load DATA for TH0
  assign th0_in  = timer_data_in;

// Count enable for TL0
  assign e_tl0  = (ena_t0 == 0)               ? 0            :
                  ((t0_gated_n | gate0) == 0) ? 0            :
                  (ct0 == 1)                  ? t0_event     :
                  (t0m == 0)                  ? clk_div12_t0 :
                                              clk_div4;

// Count enable for TH0
  assign e_th0  = (mode0  == `t0_13_bit)      ? tl0_sat5       :
                  (mode0  == `t0_16_bit)      ? tl0_sat8       :
                  // mode0 = t0_2x8_bit
                  (mode0  == `t0_auto_reload) ? 0              :
                  (ena_t1 == 0)               ? 0              :
                  (t0m    == 0)               ? clk_div12_t0_h :
                                                clk_div4;
                  // (when t0m = 1)

// Parallel load control for TL1
  assign ld_tl1_n = (tl1_wr == 1)               ? 0         :
                    (mode1  == `t1_auto_reload) ? ~tl1_sat8 :
                                                  1;

// Parallel load control for TH1
  assign ld_th1_n = (th1_wr == 1) ? 0 : 1;

// Parallel load DATA for TL1
  assign tl1_in  = (tl1_wr == 1) ? timer_data_in : th1_reg;

// Parallel load DATA for TH1
  assign th1_in  = timer_data_in;

// Count enable for TL1
  assign e_tl1  = ((ena_t1 == 0) & (mode0 != `t0_2x8_bit)) ? 0            :
                  (mode1 == `t1_off)                       ? 0            :
                  ((t1_gated_n | gate1) == 0)              ? 0            :
                  (ct1   == 1)                             ? t1_event     :
                  (t1m   == 0)                             ? clk_div12_t1 :
                                                             clk_div4;
// Count enable for TH1
  assign e_th1  = (mode1 == `t1_13_bit) ? tl1_sat5 :
                  (mode1 == `t1_16_bit) ? tl1_sat8 :
                                          0;	// when mode1 = t1_auto_reload
                                                //   or mode1 = t1_off

// The count-enables for TH0/TL0 and TH1/TL1 are active in the C2 clock phase.
// Thus, all the timer/ctr modules will change states at the end of the C2
// clock phase.  This enables the CPU to read these registers in the C3 phase
// of the same machine cycle.

  DW8051_timer_ctr #(8) i1			// Timer/Ctr for TL0
                     (.q         (tl0_reg),
                      .q_n       (tl0_reg_n),	//not used
                      .ones_all  (tl0_sat8),
                      .ones_5lsb (tl0_sat5),
                      .clk       (clk),
                      .rst_n     (rst_n),
                      .ld_n      (ld_tl0_n),
                      .data_in   (tl0_in),
                      .cnt_en    (e_tl0));

  DW8051_timer_ctr #(8) i2			// Timer/Ctr for TH0
                     (.q         (th0_reg),
                      .q_n       (th0_reg_n),	//not used
                      .ones_all  (th0_sat8),
                      .ones_5lsb (th0_sat5),	// not used
                      .clk       (clk),
                      .rst_n     (rst_n),
                      .ld_n      (ld_th0_n),
                      .data_in   (th0_in),
                      .cnt_en    (e_th0));

  DW8051_timer_ctr #(8) i3			// Timer/Ctr for TL1
                     (.q         (tl1_reg),
                      .q_n       (tl1_reg_n),	//not used
                      .ones_all  (tl1_sat8),
                      .ones_5lsb (tl1_sat5),
                      .clk       (clk),
                      .rst_n     (rst_n),
                      .ld_n      (ld_tl1_n),
                      .data_in   (tl1_in),
                      .cnt_en    (e_tl1));

  DW8051_timer_ctr #(8) i4			// Timer/Ctr for TH1
                     (.q         (th1_reg),
                      .q_n       (th1_reg_n),	//not used
                      .ones_all  (th1_sat8),
                      .ones_5lsb (th1_sat5),	// not used
                      .clk       (clk),
                      .rst_n     (rst_n),
                      .ld_n      (ld_th1_n),
                      .data_in   (th1_in),
                      .cnt_en    (e_th1));


// Divide-by-4 clock is high only in cycle C2
  assign clk_div4  = (cycle == `c2) ? 1 : 0;

// Divide-by-12 clock process
// The "count", clk_div12_t0, clk_div12_t0_h and clk_div12_t1 are updated in the
// beginning of the C2 clock phase.
  always @(posedge clk or negedge rst_n)
  begin : clk_div_process
    if (rst_n == 0)
    begin 
      count_t0       <= 2'b00;
      count_t1       <= 2'b00;
      count_t0_h     <= 2'b00;
      clk_div12_t0   <= 1;
      clk_div12_t1   <= 1;
      clk_div12_t0_h <= 1;
    end
    else
    begin
      if (ena_t0 == 0)
      begin 
        count_t0     <= 2'b00;
        clk_div12_t0 <= 1;
      end
      else if (cycle == 2'b00)
      begin 
        count_t0[0]  <= ~(count_t0[0] | count_t0[1]);
        count_t0[1]  <= count_t0[0];
        clk_div12_t0 <= count_t0[1];
      end
      else clk_div12_t0 <= 0;


      if ((mode0 == `t0_2x8_bit) && (ena_t1 == 0))
      begin
        count_t0_h     <= 2'b00;
        clk_div12_t0_h <= 1;
      end
      else if (cycle == 2'b00)
      begin
        count_t0_h[0]  <= ~(count_t0_h[0] | count_t0_h[1]);
        count_t0_h[1]  <= count_t0_h[0];
        clk_div12_t0_h <= count_t0_h[1];
      end
      else clk_div12_t0_h <= 0;


      if (((mode0 != `t0_2x8_bit) && (ena_t1 == 0)) || (mode1 == `t1_off))
      begin 
        count_t1     <= 2'b00;
        clk_div12_t1 <= 1;
      end
      else if (cycle == 2'b00)
      begin 
        count_t1[0]  <= ~(count_t1[0] | count_t1[1]);
        count_t1[1]  <= count_t1[0];
        clk_div12_t1 <= count_t1[1];
      end
      else clk_div12_t1 <= 0;
    end 
  end  //clk_div_process


// Defining the Timer 1 overflow conditions
  assign t1_ofl_i = ((mode1 == `t1_13_bit) | (mode1 == `t1_16_bit)) ? th1_sat8 :
                    (mode1 == `t1_auto_reload)                      ? tl1_sat8 :
                                                                      0;
                     // when  mode1 = t1_off

// Defining the Timer 1 overflow conditions
  assign t0_ofl_i = ((mode0 == `t0_13_bit) | (mode0 == `t0_16_bit)) ? th0_sat8 :
                                                                      tl0_sat8;
                    // low byte overflow is output in auto-reload mode
                    // and in 2x8 bit mode!


  // output signals
  assign timer_data_out = (tmod_cs == 1) ? tmod_reg :
                          (th0_cs  == 1) ? th0_reg  :
                          (th1_cs  == 1) ? th1_reg  :
                          (tl0_cs  == 1) ? tl0_reg  :
                                           tl1_reg;

  assign  timer_sfr_cs  = tmod_cs | th0_cs | th1_cs | tl0_cs | tl1_cs;

  assign tf0_set  = (mode0 == `t0_13_bit) ? th0_sat8 :
                    (mode0 == `t0_16_bit) ? th0_sat8 :
                                            tl0_sat8;
                    // when mode0 = t0_2x8_bit
                    //   or mode0 = t0_auto_reload

  assign tf1_set = (mode0 == `t0_2x8_bit) ? th0_sat8 : t1_ofl_i;
  assign t1_ofl  = t1_ofl_i;


// t0_out and t1_out are 1 clock delayed versions of t0_ofl_i and t1_ofl_i
// respectively.
  always @(posedge clk or negedge rst_n)
   begin : out_process
    if (rst_n == 0)
    begin 
      t0_out <= 0;
      t1_out <= 0;
    end
    else
    begin
      t0_out <= t0_ofl_i;
      t1_out <= t1_ofl_i;
    end 
  end  //out_process

endmodule