dw8051_core.v

DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.

// $Id: DW8051_core.v,v 1.1 1996/07/25 17:42:36 gina Exp $
//------------------------------------------------------------------------------
//
//        This confidential and proprietary software may be used only
//     as authorized by a licensing agreement from Synopsys Inc.
//     In the event of publication, the following notice is applicable:
//
//                    (C) COPYRIGHT 1996   SYNOPSYS INC.
//                          ALL RIGHTS RESERVED
//
//        The entire notice above must be reproduced on all authorized
//        copies.
//
// FILE: DW8051_core.v
//
// AUTHOR: Ludwig Rieder
//
// ABSTRACT: DW8051 core module (Verilog version)
//
// MODIFICATION HISTORY:
//      L.Rieder        10.06.96        Verilog version created
//	L.Rieder	17.07.96	ri0,ti0,ri1,ti1 = 0 if modules not
//					present
//
//      Gina Ngo        11.20.96        Fixed star 38722: added header
//	Bala Needamangalam
//			Dec 20.97	Internal RAM and ROM interface signals
//					added to core I/Os. Internal ROM 
//					instantiation removed. Translated from
//					Ludwig's VHDL changes.
//                      July 20,1999    Removed all DesignWare-Foundation 
//                                      license checkout commands.
//------------------------------------------------------------------------------


`include "./DW8051/DW8051_package.inc"
`include "./DW8051/DW8051_parameter.v"


module DW8051_core (clk, 
		    por_n,
                    rst_in_n,
                    rst_out_n,
                    test_mode_n,

                    stop_mode_n,
                    idle_mode_n,
    
                    sfr_addr,
                    sfr_data_out,
                    sfr_data_in,
                    sfr_wr,
                    sfr_rd,

                    mem_addr,
                    mem_data_out,
                    mem_data_in,
                    mem_wr_n,
                    mem_rd_n,
                    mem_pswr_n,
                    mem_psrd_n,
                    mem_ale,
                    mem_ea_n,

                    int0_n,		// External Interrupt 0, std
                    int1_n,		// External Interrupt 1, std
                    int2,		// External Interrupt 2, ext
                    int3_n,		// External Interrupt 3, ext
                    int4,		// External Interrupt 4, ext
                    int5_n,		// External Interrupt 5, ext

                    pfi,		// power fail interrupt, ext
                    wdti,		// watchdog timer intr, ext

                    rxd0_in,		// serial port 0 input
                    rxd0_out,		// serial port 0 output
                    txd0,		// serial port 0 output

                    rxd1_in,		// serial port 1 input
                    rxd1_out,		// serial port 1 output
                    txd1,		// serial port 1 output

                    t0,			// Timer 0 external input
                    t1,			// Timer 1 external input
                    t2,			// Timer/Counter2 ext.input
                    t2ex,		// Timer/Counter2 capt./reload
                    t0_out,		// Timer/Counter0 ext. output
                    t1_out,		// Timer/Counter1 ext. output
                    t2_out,		// Timer/Counter2 ext. output

                    port_pin_reg_n,
                    p0_mem_reg_n,
                    p0_addr_data_n,
                    p2_mem_reg_n,

		    iram_addr,
		    iram_data_out,
		    iram_data_in,
		    iram_rd_n,
		    iram_we1_n,
		    iram_we2_n,

		    irom_addr,
		    irom_data_out,
		    irom_rd_n,
		    irom_cs_n
// synopsys dc_script_begin
// set_design_license  {DesignWare-Foundation} -quiet
// synopsys dc_script_end
		    );

 input clk;
 input por_n;
 input rst_in_n;
 input test_mode_n;
 input [7:0] sfr_data_in;
 input [7:0] mem_data_in;
 input mem_ea_n;
 input int0_n;
 input int1_n;
 input int2;
 input int3_n;
 input int4;
 input int5_n;
 input pfi;
 input wdti;
 input rxd0_in;
 input rxd1_in;
 input t0;
 input t1;
 input t2;
 input t2ex;
 input [7:0] iram_data_out;
 input [7:0] irom_data_out;
 output rst_out_n;
 output stop_mode_n;
 output idle_mode_n;
 output [7:0] sfr_addr;
 output [7:0] sfr_data_out;
 output sfr_wr;
 output sfr_rd;
 output [15:0] mem_addr;
 output [7:0]  mem_data_out;
 output mem_wr_n;
 output mem_rd_n;
 output mem_pswr_n;
 output mem_psrd_n;
 output mem_ale;
 output rxd0_out;
 output txd0;
 output rxd1_out;
 output txd1;
 output t0_out;
 output t1_out;
 output t2_out;
 output port_pin_reg_n;
 output p0_mem_reg_n;
 output p0_addr_data_n;
 output p2_mem_reg_n;
 output [7:0] iram_addr;
 output [7:0] iram_data_in;
 output iram_rd_n;
 output	iram_we1_n;
 output iram_we2_n;
 output [15:0] irom_addr;
 output irom_rd_n;
 output irom_cs_n;

//------------------------------------------------------------------------------
wire clk;
wire por_n;
wire rst_in_n;
wire test_mode_n;
wire [7:0] sfr_data_in;
wire [7:0] mem_data_in;
wire mem_ea_n;
wire int0_n;
wire int1_n;
wire int2;
wire int3_n;
wire int4;
wire int5_n;
wire pfi;
wire wdti;
wire rxd0_in;
wire rxd1_in;
wire t0;
wire t1;
wire t2;
wire t2ex;
wire rst_out_n;
wire stop_mode_n;
wire idle_mode_n;
wire [7:0] sfr_addr;
wire [7:0] sfr_data_out;
wire sfr_wr;
wire sfr_rd;
wire [15:0] mem_addr;
wire [7:0]  mem_data_out;
wire mem_wr_n;
wire mem_rd_n;
wire mem_pswr_n;
wire mem_psrd_n;
wire mem_ale;
wire rxd0_out;
wire txd0;
wire rxd1_out;
wire txd1;
wire t0_out;
wire t1_out;
wire t2_out;
wire port_pin_reg_n;
wire p0_mem_reg_n;
wire p0_addr_data_n;
wire p2_mem_reg_n;


//---------------
// local signals:
//---------------
wire low;
 
wire t_rst_out_n;
 
wire timer2_sfr_cs;
wire t_timer2_sfr_cs;
wire [7:0] timer2_data_out;
wire [7:0] t_timer2_data_out;
wire t_t2_out;

wire serial0_sfr_cs;
wire t_serial0_sfr_cs;
wire [7:0] serial0_data_out;
wire [7:0] t_serial0_data_out;
wire serial1_sfr_cs;
wire t_serial1_sfr_cs;
wire [7:0] serial1_data_out;
wire [7:0] t_serial1_data_out;
 
wire [7:0] int_sfr_addr;
wire [7:0] int_sfr_data_out;
wire [7:0] int_sfr_data_in;
wire int_sfr_wr;
wire int_sfr_cs;
 
wire [15:0] t_mem_addr;
wire [7:0]  t_mem_data_out;
wire t_mem_psrd_n;
 
wire timer_sfr_cs;
wire [7:0] timer_data_out;
 
wire intr_sfr_cs;
wire [7:0] intr_data_out;
wire       intr_sfr_cs_0;
wire [7:0] intr_data_out_0;
wire       intr_sfr_cs_1;
wire [7:0] intr_data_out_1;
 
wire [2:0] tm;
wire t0m, t1m, t2m;

wire ena_t0;
wire ena_t1;
wire ena_t0_0;
wire ena_t1_0;
wire ena_t0_1;
wire ena_t1_1;

wire tf0_set, tf1_set;
wire t1_ofl;

wire rclk, tclk;
wire t_rclk, t_tclk;
wire t2_ofl;
wire t_t2_ofl;
wire tf2, exf2;
wire t_tf2, t_exf2;

wire smod0;
wire ri0, ti0;
wire t_ri0, t_ti0;
wire ri1, ti1;
wire t_ri1, t_ti1;
wire t_rxd0_out;
wire t_txd0;
wire t_rxd1_out;
wire t_txd1;

wire smod1;
wire smod1_0;
wire smod1_1;
 
wire [1:0] cpu_cycle;
wire cpu_int_req;
wire [3:0] cpu_int_src;
wire cpu_int_ack;
wire cpu_int_clr;
 
wire       cpu_int_req_0;
wire [3:0] cpu_int_src_0;
wire       cpu_int_req_1;
wire [3:0] cpu_int_src_1;
 
wire [15:0] irom_addr;
wire irom_rd_n;
wire irom_cs_n;
wire [7:0] int_rom_data_out;
wire int_rom_rd_n;
wire int_rom_cs_n;

//------------------------------------------------------------------------------