dw8051_control.v

DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.

                      case (cycle)
                        `c2 : begin
                                dest <= t_dest;
                                if (act_instr[4] == 1)
                                begin 
                                  // POP, (SP) <- (SP) - 1
                                  sp_cnt_dir <= 0;	// down
                                  cnt_sp     <= 1;
                                end 
                              end
                        `c3 : cnt_sp <= 0;
                        default: begin end
                      endcase
                    end
                default: begin end
              endcase
            end
        8 : begin				// MOVX @DPTR,A / MOVX A,@DPTR
              case (instr_cycle)		// MOVX @R1,A   / MOVX A,@Ri
                0 : begin
                      case (cycle)
                        `c2 : begin
                                if (act_instr[4] == 1)
                                begin
                                  // MOVX @DPTR,A / MOVX @Ri,A
                                  dest <= t_dest;
                                end 
                              end
                        default: begin end
                      endcase
                    end
                1 : begin
                      case (cycle)
                        `c2 : begin
                                wait_for_ram <= 1;	// stay here
                                auto_inc_pc  <= 0;
                              end
                        `c3 : begin
                                if (biu_ram_access_rdy == 1)
                                begin 
                                  if (act_instr[4] == 0)
                                  begin 
                                    // MOVX A,@DPTR / MOVX A,@Ri
                                    // set of dest allowed here
                                    dest <= t_dest;
                                  end 
                                  wait_for_ram <= 0;
                                end 
                              end
                        default: begin end
                      endcase
                    end
                default: begin end
              endcase
            end
     // three cycle instructions:
        9 : begin				// MOV direct,direct
              case (instr_cycle)		// (3 Bytes)
                2 : begin
                      case (cycle)
                        `c2 : dest <= t_dest;
                        default: begin end
                      endcase
                    end
                default: begin end
              endcase
            end
        10 : begin				// MOV direct,#data
               case (instr_cycle)		// (3 Bytes)
                 1 : begin
                       case (cycle )
                         `c2 : dest <= t_dest;
                         default: begin end
                       endcase
                     end
                 2 : begin
                       case (cycle )
                         `c2 : dest <= t_dest;
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        11 : begin					// ANL,ORL,XRL (3 Bytes)
               case (instr_cycle)
                 1 : begin
                       case (cycle)
                         `c2 : dest  <= t_dest;
                         default: begin end
                       endcase
                     end
                 2 : begin
                       case (cycle)
                         `c2 : begin
                                 temp2 <= biu_instr;    // #data
                                 dest  <= t_dest;
                                 sfr_rd = 1;            // STAR 49995 fix
				 // read in RAM is not necessary, cannot
				 // have changed meanwhile.
                               end
                         `c3 : begin                    // STAR 49995 fix
                                 sfr_rd = 0;            // STAR 49995 fix
                                 temp1 <= sfr_data_in;  // STAR 49995 fix
                               end
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        12 : begin					// INC DPTR
               case (instr_cycle)
                 0 : begin
                       case (cycle)
                         `c2 : begin
                                 auto_inc_pc <= 0;
                                 dp_inc      <= 8'b00000001;
                               end
                         default: begin end
                       endcase
                     end
                 1 : begin
                       case (cycle)
                         `c2 : begin
                                 sel_pc_dptr_n <= 0;	// dptr
                                 dest          <= t_dest;
                               end
                         default: begin end
                       endcase
                     end
                 2 : begin
                       case (cycle)
                         `c2 : begin
                                 sel_pc_dptr_n <= 0;	// dptr
                                 dest          <= t_dest;
                               end
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        13 : begin					// DNJZ Rn,rel
               case (instr_cycle)
                 0 : begin
                       case (cycle)
                         `c2 : dest  <= t_dest;
                         default: begin end
                       endcase
                     end
                 1 : begin
                       case (cycle)
                         `c1 : pc_inc  <= biu_instr;
                         `c2 : auto_inc_pc  <= 0;
                         `c3 : begin
                                 if (alu_zero == 0)
                                 begin 
                                   result   <= new_pc;
                                   set_pc_n <= 0;
                                 end 
                               end
                         `c4 : set_pc_n <= 1;
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        14 : begin					// ACALL
               case (instr_cycle)
                 0 : begin
                       case (cycle)
                         // increment sp before writing to @sp:
                         `c2 : begin
                                 sp_cnt_dir <= 1;		// up
                                 cnt_sp     <= 1;
                                 pc_inc     <= 8'b00000001;	// 1
                               end
                         `c3 : begin
                                 cnt_sp <= 0;
                                 temp1  <= new_pc[7:0];
                               end
                         default: begin end
                       endcase
                     end
                 1 : begin
                       case (cycle)
                         `c1 : pc_inc <= 8'b00000000;		// 0
                         `c2 : dest <=  12;			// @sp
                         `c3 : begin
                                 result[15:11] <= new_pc[15:11];
                                 result[10: 8] <= act_instr[7:5];
                                 result[ 7: 0] <= biu_instr;
                                 set_pc_n      <= 0;
                               end
                         `c4 : begin
                                 set_pc_n <= 1;
                                 temp1    <= new_pc[15:8];
                               end
                         default: begin end
                       endcase
                     end
                 2 : begin
                       case (cycle)
                         `c1 : cnt_sp  <= 1;
                         `c2 : begin
                                 cnt_sp <= 0;
                                 dest   <= 12;		// @sp
                               end
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        15 : begin					// AJMP
               case (instr_cycle)
                 1 : begin
                       case (cycle)
                         `c2 : pc_inc  <= 8'b00000000;	// STAR 54739 fix.
                         `c3 : begin
                                 result[15:11] <= new_pc[15:11];
                                 result[10: 8] <= act_instr[7:5];
                                 result[ 7: 0] <= biu_instr;
                                 set_pc_n      <= 0;
                               end
                         `c4 : begin
                                 set_pc_n <= 1;
                               end
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        16 : begin					// SJMP
               case (instr_cycle)
                 1 : begin
                       case (cycle)
                         `c1 : pc_inc      <= biu_instr;
                         `c2 : auto_inc_pc <= 0;
                         `c3 : begin
                                 result   <= new_pc;
                                 set_pc_n <= 0;
                               end
                         `c4 : set_pc_n  <= 1;
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        17 : begin					// JMP @A+DPTR
               case (instr_cycle)
                 0 : begin
                       case (cycle)
                         `c2 : auto_inc_pc <= 0;	// stay
                         default: begin end
                       endcase
                     end
                 1 : begin
                       case (cycle)
                         `c2 : begin
                                 sel_pc_dptr_n <= 0;	// dptr
                                 dp_inc        <= acc;
                               end
                         `c3 : begin
                                 result   <= new_pc;
                                 set_pc_n <= 0;
                               end
                         `c4 : set_pc_n <= 1;
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        18 : begin					// JNZ,JZ,JC,JNC
               case (instr_cycle)
                 1 : begin
                       case (cycle)
                         `c1 : pc_inc  <= biu_instr;
                         `c2 : auto_inc_pc  <= 0;
                         `c3 : begin
                                 if ( ((act_instr[5] == 1) &&
                                       (act_instr[4] != alu_zero)) ||
                                       // (JZ,JNZ)
                                      ((act_instr[5] == 0) &&
                                       (act_instr[4] != psw[7])))
                                       // (JC,JNC)
                                 begin 
                                   result   <= new_pc;
                                   set_pc_n <= 0;
                                 end 
                               end
                         `c4 : set_pc_n <= 1;
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        19 : begin					// MOVC
               case (instr_cycle)
                 0 : begin
                       case (cycle)
                         `c2 : auto_inc_pc <= 0;
                         default: begin end
                       endcase
                     end
                 1 : begin
                       case (cycle)
                         `c2 : begin
                                 if (act_instr[4] == 1)
                                 begin 
                                   // MOVC A,@A+DPTR
                                   sel_pc_dptr_n <= 0;
                                   dp_inc        <= acc;
                                 end
                                 else
                                 begin
                                   // MOVC A,@A+PC
                                   sel_pc_dptr_n <= 1;
                                   pc_add_signed <= 0;	// unsigned
                                   pc_inc        <= acc;
                                 end 
                               end
                         default: begin end
                       endcase
                     end
                 2 : begin
                       case (cycle)
                         `c2 : dest <= t_dest;
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
        20 : begin					//  MOV DPTR,#data16
               case (instr_cycle)
                 1 : begin
                       case (cycle)
                         `c2 : dest <= t_dest;
                         default: begin end
                       endcase
                     end
                 2 : begin
                       case (cycle)
                         `c2 : dest <= t_dest;
                         default: begin end
                       endcase
                     end
                 default: begin end
               endcase
             end
     // four cycle instructions:
        21 : begin					// JB,JNB,JBC
               case (instr_cycle)
                 2 : begin
                       case (cycle)
                         `c1 : pc_inc  <= biu_instr;
                         `c2 : begin
                                 auto_inc_pc <= 0;
                                 if ( ((act_instr[5] =