dw8051_control.v

DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.

                           biu_wr_ram_addr_h <= 0;
                           biu_wr_ram_addr_l <= 0;
                         end
                   default: begin end
                 endcase
               end
          // 15: src ext.RAM, @DPTR
          15 : begin
                 case (cycle)
                   `c3 : begin
                           biu_ram_addr      <= dptr;
                           biu_wr_ram_addr_h <= 1;	// 16 bit
                           biu_wr_ram_addr_l <= 1;
                           biu_rd_ram        <= 1;
                         end
                   `c4 : begin
                           biu_wr_ram_addr_h <= 0;
                           biu_wr_ram_addr_l <= 0;
                         end
                   default: begin end
                 endcase
               end
          default: begin end
        endcase
      end  // source sequencer



      //--------------------------------------------------------------
      // destination sequencer:
      // dest should be set latest in c2 !
      // Data is written always in c1 (of the next instruction cycle).
      // For an indirect write the address is fetched in c4.
      // sfr_data_out must be set at last in c4, in c1 there may be new
      // data (new instr).
      //--------------------------------------------------------------
      case (dest)
        // 1: dest accumulator
        1 : begin
              case (cycle)
                `c3 : begin
                        sfr_addr = `acc_addr;
                      end
                `c4 : begin
                        sfr_data_out = alu;
                        sfr_wr       = 1;
                      end
                default: begin end
              endcase
            end
        // 2: dest register
        2 : begin
              case (cycle)
                `c3 : begin
                        sfr_addr = {3'b000, rs, act_instr[2:0]};
                        ram128_wr_addr_val_n <= 0;
                      end
                `c4 : begin
                        sfr_data_out  = alu;
                        ram128_wr_n  <= 0;
                      end
                default: begin end
              endcase
            end
        // 3: dest direct
        3 : begin
              case (cycle)
                `c3 : begin
                        sfr_addr = biu_instr;
                        if (biu_instr[7] == 0)
                          ram128_wr_addr_val_n <= 0;
                      end
                `c4 : begin
                        sfr_data_out = alu;
                        if (sfr_addr[7] == 0)		//  sfr_addr ! for
                        begin				// exit of idle_mode
                          ram128_wr_n <= 0;
                        end 
			else
                          sfr_wr = 1;			

                        // check for access to PCON (idle/stop mode)
                        // and IE/IP/EIE/EIP (for int_delay, done
                        // here also for DJNZ)
                        // PSW check also here
                        case (biu_instr )
                          `psw_addr : rs <= alu[4:3];
                          `pcon_addr: begin
                                        if (alu[0] == 1)
                                        begin 
                                          if (t_int_ack == 1)
                                            // avoid set of idle_mode:
                                            sfr_data_out = {alu[7:1], 1'b0};
                                          else
                                            idle_mode_n <= 0;
                                        end 
                                        if (alu[1] == 1)
                                          stop_mode_n <= 0;
                                      end
                          `ie_addr,
                          `ip_addr  : begin
                                        if (act_instr == 8'b11010101)
                                          // DJNZ direct,rel
                                          int_delay <= 1;
                                      end
                          `eie_addr,
                          `eip_addr : begin
                                        if ((eie_eip_check == 1) &
                                            (act_instr == 8'b11010101))
                                          // DJNZ direct,rel
                                          int_delay <= 1;
                                      end
                          default: begin end
                        endcase
                      end
                default: begin end
              endcase
            end
        // 4: dest indirect
        4 : begin
              case (cycle)
                `c3 : begin
                        sfr_addr = indir_addr;
                        if (indir_addr[7] == 0)
                          ram128_wr_addr_val_n <= 0;
                        else
                          ram256_wr_addr_val_n <= 0;
                      end
                `c4 : begin
                        sfr_data_out = alu;
                        if (indir_addr[7] == 0)
                          ram128_wr_n <= 0;
                        else
                          ram256_wr_n <= 0;
                      end
                default: begin end
              endcase
            end
        // 5: dest accumulator direct (src biu_data_in)
        5 : begin
              case (cycle)
                `c4 : ld_acc_direct <= 1;
                default: begin end
              endcase
            end
        //  6: dest ext.RAM, @Ri
        6 : begin
              case (instr_cycle)
                0 : begin
                      case (cycle)
                        `c3 : begin
                                biu_wr_ram_addr_l <= 1;		// 8 bit
                                biu_wr_ram        <= 1;
                              end
                        `c4 : begin
                                biu_wr_ram_addr_l <= 0;
                                biu_ram_addr      <= {mpage, alu};
                                biu_data_out      <= acc;
                              end
                        default: begin end
                      endcase
                    end
                default: begin end
              endcase
            end
        // 7: dest bit, instr_cycle=1
        7 : begin
              case (instr_cycle)
                1,
                2 : begin
                      case (cycle)
                        `c3 : begin
                                if (bit_nr[7] == 0)
                                begin 
                                  // area 20..2F
                                  sfr_addr = {4'b0010, bit_nr[6:3]};
                                  ram128_wr_addr_val_n <= 0;
                                end
                                else
                                  // SFR's
                                  sfr_addr = {bit_nr[7:3], 3'b000};
                              end
                        `c4 : begin
                                sfr_data_out = alu;
                                if (bit_nr[7] == 0)
                                begin 
                                  ram128_wr_n <= 0;
                                end 
				else 
                                  sfr_wr = 1;

                                // check for access to PSW:
                                if (sfr_bit_addr == `psw_addr)
                                  rs <= alu[4:3];
                              end
                        default: begin end
                      endcase
                    end
                default: begin end
              endcase
            end
        // 8: dest direct, address in 2nd Byte, data in 3rd Byte
        8 : begin
              case (instr_cycle)
                1 : begin
                      case (cycle)
                        `c3 : sfr_addr = biu_instr;
                        default: begin end
                      endcase
                    end
                2 : begin
                      case (cycle)
                        `c3 : begin
                                if (sfr_addr[7] == 0)
                                  ram128_wr_addr_val_n <= 0;
                              end
                        `c4 : begin
                                sfr_data_out = alu;
                                if (sfr_addr[7] == 0)
                                begin 
                                  ram128_wr_n <= 0;
                                end 
                                else 
				  sfr_wr = 1;

                                // check for access to PCON and PSW:
                                case (t_sfr_addr )
                                  `psw_addr  : rs <= alu[4:3];
                                  `pcon_addr : begin
                                                 if (alu[0] == 1)
                                                 begin 
                                                   if (t_int_ack == 1)
                                                     // avoid set of idle_mode:
                                                     sfr_data_out = {alu[7:1],
                                                                     1'b0};
                                                   else
                                                     idle_mode_n <= 0;
                                                 end 
                                                 if (alu[1] == 1)
                                                   stop_mode_n <= 0;
                                               end
                                  default: begin end
                                endcase
                              end
                        default: begin end
                      endcase
                    end
                default: begin end
              endcase
            end
        // 9: dest direct, data in acc, address xch_addr
        9 : begin
              case (cycle)
                `c3 : begin
                        sfr_addr = xch_addr;
                        if (xch_addr[7] == 0)
                          ram128_wr_addr_val_n <= 0;
                      end
                `c4 : begin
                        sfr_data_out = acc;
                        if (xch_addr[7] == 0)
                        begin 
                          ram128_wr_n <= 0;
                        end 
                        else 
			  sfr_wr    = 1;
                        acc_data <= alu;
                        ld_acc   <= 1;

                        // check for access to PCON (idle/stop mode)
                        // and PSW (rs)
                        case (xch_addr)
                          `psw_addr  : rs <= temp2[4:3];
                          `pcon_addr : begin
                                         if (acc[0] == 1)
                                         begin 
                                           if (t_int_ack == 1)
                                             // avoid set of idle_mode:
                                             sfr_data_out = {acc[7:1], 1'b0};
                                           else
                                             idle_mode_n <= 0;
                                         end 
                                         if (acc[1] == 1)
                                           stop_mode_n <= 0;
                                       end
                          default: begin end
                        endcase
                      end
                default: begin end
              endcase
            end
        // 10: dest indirect, data in acc, address xch_addr
        10 : begin
               case (cycle)
                 `c3 : begin
                         sfr_addr = xch_addr;
                         if (xch_addr[7] == 0)
                           ram128_wr_addr_val_n <= 0;
                         else
                           ram256_wr_addr_val_n <= 0;
                       end
                 `c4 : begin
                         sfr_data_out = acc;
                         if (xch_addr[7] == 0)
                           ram128_wr_n <= 0;
                         else
                         begin
                           ram256_wr_n <= 0;
                         end 
                         acc_data <= alu;
                         ld_acc   <= 1;
                       end
                 default: begin end
               endcase
             end
        // 11: dest indirect, data(7:4) in alu, data(3:0) in acc,
        // address xch_addr
        11 : begin
               case (cycle)
                 `c3 : begin
                         sfr_addr = xch_addr;
                         if (xch_addr[7] == 0)
                           ram128_wr_addr_val_n <= 0;
                         else
                           ram256_wr_addr_val_n <= 0;
                       end
                 `c4 : begin
                         sfr_data_out = {alu[7:4], acc[3:0]};
                         if (xch_addr[7] == 0)
                           ram128_wr_n <= 0;
                         else
                          begin
                           ram256_wr_n <= 0;
                         end 
                         // load accu direct:
                         acc_data <= {acc[7:4], alu[3:0]};
                         ld_acc   <= 1;
                       end
                 default: begin end
               endcase
             end
        // 12: dest @SP
        12 : begin
               case (cycle)
                 `c3 : begin
                         sfr_addr = sp;
                         if (sp[7] == 0)
                           ram128_wr_addr_val_n <= 0;
                         else
                           ram256_wr_addr_val_n <= 0;
                       end
                 `c4 : begin
                         sfr_data_out = alu;
                         if (sp[7] == 0)
                           ram128_wr_n <= 0;
                         else
                           ram256_wr_n <= 0;
                       end
                 default: begin end
               endcase
             end
        // 13: dest dptr
        13,
        14 : begin
               case (instr_cycle)
                 1 : begin