dw8051_control.v

DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.

wire [15:0] dptr;
wire [ 7:0] indir_data_in;
wire [15:0] pc;
wire [15:0] add16_sum;
wire eie_eip_check;
wire [ 7:0] mpage;
wire [ 4:0] dec_itype;		// 0..31
wire [ 2:0] dec_last_cycle;	// 0..7
wire [ 3:0] dec_src;		// 0..15
wire [ 1:0] dec_src_cycle;	// 0..3
wire [ 3:0] dec_dest;		// 0..15
wire [ 5:0] dec_alu_op;
wire dec_chg_flags;
wire dec_rmw;
wire alu_zero;
wire alu_equal;
wire bit_status;
wire [ 7:0] sfr_data_in;
wire cpu_idle_mode_n;
wire cpu_stop_mode_n;

reg  [15:0] biu_ram_addr;
reg  biu_wr_ram_addr_h;
reg  biu_wr_ram_addr_l;
reg  [ 7:0] biu_data_out;
reg  biu_wr_ram;
reg  biu_rd_ram;
reg  biu_rd_rom;
reg  [ 7:0] ram_addr;
reg  ram128_wr_addr_val_n;
reg  ram256_wr_addr_val_n;
reg  [ 7:0] ram_data_in;
reg  ram128_wr_n;
reg  ram256_wr_n;
reg  ram_rd_n;
wire [ 7:0] int_sfr_addr;
reg  [ 7:0] int_sfr_data_out;
reg  int_sfr_wr;
reg  [ 7:0] ext_sfr_addr;
reg  [ 7:0] ext_sfr_data_out;
reg  ext_sfr_wr;
reg  ext_sfr_rd;
reg  port_pin_reg_n;
wire int_ack;
reg  int_clr;
reg  int_rec;
wire [ 7:0] cpu_temp1;
wire [ 7:0] cpu_temp2;
wire [ 7:0] cpu_temp3;
reg  [15:0] result;
reg  pc_cnt_dir;
reg  inc_pc;
reg  set_pc_n;
reg  [ 7:0] pc_inc;
reg  [ 7:0] dp_inc;
reg  pc_add_signed;
reg  sel_pc_dptr_n;
reg  sp_cnt_dir;
reg  cnt_sp;
reg  [ 5:0] alu_op;
reg  chg_flags;
reg  [ 7:0] acc_data;
reg  ld_acc;
reg  ld_acc_direct;
wire [ 7:0] cpu_bit_nr;

//---------------
// local signals:
//---------------
reg  [ 4:0] itype;		// 0..31
 
reg  stop_mode_n;
reg  idle_mode_n;
reg  idle_mode_del_n;
 
reg  [ 7:0] t_sfr_addr;
reg  [ 7:0] indir_addr;
wire [ 7:0] sfr_bit_addr;
reg  [ 7:0] xch_addr;
reg  [ 1:0] rs;			// Register select
 
reg  [ 7:0] act_instr;
reg  [ 2:0] instr_cycle;	// 0..7
 
reg  [ 7:0] temp1;
reg  [ 7:0] temp2;
reg  [ 7:0] temp3;
 
reg  [ 2:0] last_cycle;		// 0..7
reg  [ 3:0] src;		// 0..15
reg  [ 1:0] src_cycle;		// 0..3
reg  [ 3:0] dest;		// 0..15
 
wire [15:0] new_pc;
reg  auto_inc_pc;
reg  [ 3:0] t_dest;		// 0..15
reg  wait_for_ram;
reg  int_delay;
reg  [ 3:0] int_src_rec;
reg  t_int_ack;
 
// signals for bit operations:
reg  [ 7:0] bit_nr;
 

// local variables for main_control_proc:
reg [ 7:0] sfr_addr;
reg [ 7:0] sfr_data_out;
reg sfr_wr;
reg sfr_rd;

//------------------------------------------------------------------------------
// The reg types "sfr_rd", "sfr_wr", "sfr_addr[7:0]", "sfr_data_out[7:0]" are
// used in blocking styles throughout.  In the same clocked process that these
// regs are assigned in a blocking fashion, other signals are also assigned to
// these regs.  
// The main purpose of the blocking style is as follows: each of these regs
// (e.g., sfr_wr), is assiged to TWO signals (ext_sfr_wr and int_sfr_wr) in
// the same clocked process.  Therefore, the easiest way to duplicate the
// flip-flops for the TWO signals is to use an intermediate blocking
// variable, and assign it to other signals in the *SAME* clocked process.
// The other alternative is to replace *EACH* occurrence of the blocking
// assignment of sfr_wr with TWO non-blocking assignments, one for int_sfr_wr
// and the other for ext_sfr_wr.  
//------------------------------------------------------------------------------

  assign  new_pc  = add16_sum;

  always @(posedge clk or negedge rst_n)
  begin : main_control_proc
    if (rst_n == 0)
    begin 
      idle_mode_n          <= 1;
      idle_mode_del_n      <= 1;
      stop_mode_n          <= 1;
      biu_ram_addr         <= 'b0;
      biu_wr_ram_addr_h    <= 0;
      biu_wr_ram_addr_l    <= 0;
      biu_data_out         <= 'b0;
      biu_wr_ram           <= 0;
      biu_rd_ram           <= 0;
      biu_rd_rom           <= 0;
      wait_for_ram         <= 0;
      sfr_addr              = 0;
      sfr_data_out          = 0;
      sfr_wr                = 0;
      sfr_rd                = 0;
      ram_addr             <= 'b0;
      ram128_wr_addr_val_n <= 1;
      ram256_wr_addr_val_n <= 1;
      ram_data_in          <= 'b0;
      ram128_wr_n          <= 1;
      ram256_wr_n          <= 1;
      ram_rd_n             <= 1;
      t_sfr_addr           <= 'b0;
      int_sfr_data_out     <= 'b0;
      int_sfr_wr           <= 0;
      ext_sfr_addr         <= 'b0;
      ext_sfr_data_out     <= 'b0;
      ext_sfr_wr           <= 0;
      ext_sfr_rd           <= 0;
      port_pin_reg_n       <= 0;
      indir_addr           <= 'b0;
      t_int_ack            <= 0;
      int_clr              <= 0;
      int_delay            <= 0;
      int_rec              <= 0;
      int_src_rec          <= 'b0;
      itype                <= 0;
      last_cycle           <= 0;
      src                  <= 0;
      src_cycle            <= 0;
      dest                 <= 0;
      auto_inc_pc          <= 1;
      t_dest               <=  0;
      xch_addr             <= 'b0;
      rs                   <= 'b0;
      act_instr            <= 'b0;
      instr_cycle          <=  0;
      temp1                <= 'b0;
      temp2                <= 'b0;
      temp3                <= 'b0;
      result               <= 'b0;
      pc_cnt_dir           <= 1;		// default pc dir: up
      inc_pc               <= 0;
      set_pc_n             <= 1;
      pc_inc               <= 'b0;
      dp_inc               <= 'b0;
      pc_add_signed        <= 1;
      sel_pc_dptr_n        <= 1;
      sp_cnt_dir           <= 1;		//default sp dir: up
      cnt_sp               <= 0;
      alu_op               <= 'b0;
      chg_flags            <= 0;
      acc_data             <= 'b0;
      ld_acc               <= 0;
      ld_acc_direct        <= 0;
      bit_nr               <= 'b0;
    end
    else	// posedge clk
    begin

      idle_mode_del_n <= idle_mode_n;		// simple delay

      //----------------------------------------
      // Finish read of Ri (if instr_cycle = 0):
      //----------------------------------------
      if ((instr_cycle == 0 ) && (cycle == `c2 ))
      begin 
        indir_addr  <= sfr_data_in;
        ram_rd_n    <= 1;
      end 

      //----------------------------
      // source sequencer:
      // source is read generally in
      // c1/c2 of a instr_cycle
      //----------------------------
      if (src_cycle == instr_cycle)
      begin 
        case (src)
          // 1: src accu
          1 : begin
                case (cycle)
                  `c3 : temp1  <= acc;		// src accumulator
                  default: begin end
                endcase
              end
          // 2: src register
          // 8: src register for MOVX @Ri
          2, 8 : begin				// src register
                   case (cycle)
                     `c2 : begin
                             if (src == 2)
                             begin 
                               sfr_addr  = {3'b000, rs, biu_instr[2:0]};
                               xch_addr <= {3'b000, rs, biu_instr[2:0]};
                             end
                             else
                             begin 
                               // MOVX @Ri,A
                               sfr_addr  = {3'b000, rs, 2'b00, biu_instr[0]};
                             end
			     ram_rd_n <= 0;	// must be in RAM
                           end
                     `c3 : begin
			     ram_rd_n <= 1;
                             temp1  <= sfr_data_in;
                           end
                     default: begin end
                   endcase
                 end
          // 3: src direct, src_cycle = 1
          3 : begin
                case (cycle)
                  `c1 : begin
                          xch_addr <= biu_instr;
                        end
                  `c2 : begin
                          sfr_addr = biu_instr;		// dir.addr in 2nd Byte
			  if (biu_instr[7] == 1)  
			  begin                 // Upper 128 bytes direct-
                            sfr_rd   = 1;	// accessed using sfr_rd
			  end
			  else begin		// Lower 128 bytes direct-
			    ram_rd_n <= 0;	// accessed using ram_rd_n
			  end
                        end
                  `c3 : begin
                          sfr_rd  = 0;
			  ram_rd_n <= 1;
                          temp1  <= sfr_data_in;
                        end
                  default: begin end
                endcase
              end
          //  4: src indirect, src_cycle = 0
          4 : begin
                case (cycle)
                  `c2 : begin
                          sfr_addr  = sfr_data_in;	// R0/1 content
                          xch_addr <= sfr_data_in;
			  ram_rd_n <= 0;	//indirect read 
						// only using ram_rd_n
                        end
                  `c3 : begin
			  ram_rd_n <= 1;
                          temp1  <= indir_data_in;
                        end
                  default: begin end
                endcase
              end
          // 5: src immediate
          5 : begin
                case (cycle)
                  `c3 : temp1 <= biu_instr;
                  default: begin end
                endcase
              end
          //  6: src ext.RAM, @Ri
          6 : begin
                case (cycle)
                  `c3 : begin
                          biu_ram_addr      <= {mpage, indir_addr};
                          biu_wr_ram_addr_l <= 1;	// 8 bit
                          biu_rd_ram        <= 1;
                        end
                  `c4 : begin
                          biu_wr_ram_addr_l <= 0;
                        end
                  default: begin end
                endcase
              end
          // 7: src bit, src_cycle = 1
          7 : begin
                case (cycle)
                  `c1 : begin
                          // save bit number for later (re)write:
                          bit_nr <= biu_instr;
                        end
                  `c2 : begin
                          if (biu_instr[7]== 0)
			  begin
                           // area 20..2F
                            sfr_addr = {4'b0010, biu_instr [6:3]};
			    ram_rd_n <= 0;	//accessed using ram_rd_n
			  end
                          else 
			  begin
                            // SFR's
                            sfr_addr = {biu_instr [7:3], 3'b000};
			    sfr_rd = 1;		//SFRs are accessed using sfr_rd
                          end 
                        end
                  `c3 : begin
                          sfr_rd  = 0;
			  ram_rd_n <= 1;
                          temp1  <= sfr_data_in;
                        end
                  default: begin end
                endcase
              end
          // 12: source @SP
          12 : begin
                 case (cycle)
                   `c1 : begin
                           sfr_addr = sp;
			   ram_rd_n <= 0;	//  only ram_rd_n can be used
                         end
                   `c2 : begin
			   ram_rd_n <= 1;
                           temp1  <= indir_data_in;
                         end
                   default: begin end
                 endcase
               end
          // 14: src ROM
          14 : begin
                 case (cycle)
                   `c3 : begin
                           biu_ram_addr      <= add16_sum;
                           biu_wr_ram_addr_h <= 1;	// 16 bit
                           biu_wr_ram_addr_l <= 1;
                           biu_rd_rom        <= 1;
                         end
                   `c4 : begin