dw8051_control.v

DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.

// $Id: DW8051_control.v,v 1.1 1996/07/25 17:42:30 gina Exp $
//------------------------------------------------------------------------------
//
//        This confidential and proprietary software may be used only
//     as authorized by a licensing agreement from Synopsys Inc.
//     In the event of publication, the following notice is applicable:
//
//                    (C) COPYRIGHT 1996   SYNOPSYS INC.
//                          ALL RIGHTS RESERVED
//
//        The entire notice above must be reproduced on all authorized
//        copies.
//
// FILE: DW8051_control.v
//
// AUTHOR: Ludwig Rieder
//
// ABSTRACT: DW8051 main cpu control unit (Verilog version)
//
// MODIFICATION HISTORY:
//      L.Rieder        27.10.95        Entity module created out of common
//	L.Rieder	07.05.96	port int_sfr_rd removed
//	L.Rieder	08.05.96	port sfr_wr_addr_val removed
//
//      Gina Ngo        11.20.96        Fixed star 38722: added header
//	Bala Needamangalam
//			Nov 09 97	Fix for STAR 49337: sfr_rd pulses 
//					for indirect addressed RAM read
//					accesses. The direct relationship
//					between the sfr_rd and the ram_rd_n
//					signals has been broken. The two
//					are now treated as being functionally
//					distinct.
//                      Dec 3,1997      Fix for STAR 49995. Translated from
//                                      Ludwig Rieder's VHDL version.
//      		Feb 25,98       Fix for star 51723: ram_rd_n
//                                      assignments corrected. Translated from
//					Ludwig Rieder's VHDL version.
//			March 04,98	Fix for STAR 52000. This is an extension
//					of the fix for STAR 49995, extended to
//					JBC instructions.
//			May 20, 1998	Explanation for the Blocking
//					statements used for sfr_addr, sfr_rd,
//					sfr_wr and sfr_data_out:
//					  These blocking assignments are there
//					  for the sole purpose of providing
//					  separate flip-flops for
//					  int/ext_sfr_addr, int/ext_sfr_wr
//					  etc..
//			May 20, 1998	Fix for STAR 54739: Incorrect
//					implementation of the AJMP
//					instruction:  The pc_inc value in the
//					instruction sequencer has to be made
//					0x00 for this instruction, not 0x01.
//					Else, the PC increments 3 times
//					instead of 2 as specified by the
//					instruction set architecture.
//					Even with this bug, normal operation 
//					will not be affected because bits [10:0]
//				        of the PC will be overwritten anyway.
//			May 20, 1998	- Reconditioned sfr_wr as per Ludwig's
//					recommendations, in a number of places.
//					sfr_wr is now asserted, fully
//					conditioned by the value of sfr_addr[7].
//                      July 20,1999    Removed all DesignWare-Foundation 
//                                      license checkout commands.
//------------------------------------------------------------------------------


`include "./DW8051/DW8051_package.inc"
`include "./DW8051/DW8051_parameter.v"

module DW8051_control (// standard signals:
                       clk,
                       rst_n,
                       cycle,		// act.cycle

                       // inputs:
                       biu_instr,
                       biu_ram_access_rdy,

                       int_req,
                       int_src,
    
                       alu,
                       alu_l,
                       sp,
                       dps,
                       pcon,
                       psw,
                       acc,
                       b,
                       dptr,
                       indir_data_in,
                       pc,
                       add16_sum,
                       eie_eip_check,
                       mpage,

                       dec_itype,
                       dec_last_cycle,
                       dec_src,
                       dec_src_cycle,
                       dec_dest,
                       dec_alu_op,
                       dec_chg_flags,
                       dec_rmw,

                       alu_zero,
                       alu_equal,
                       bit_status,

                       // outputs:
                       cpu_idle_mode_n,
                       cpu_stop_mode_n,
                       biu_ram_addr,
                       biu_wr_ram_addr_h,
                       biu_wr_ram_addr_l,
                       biu_data_out,
                       biu_wr_ram,
                       biu_rd_ram,
                       biu_rd_rom,

                       ram_addr,
                       ram128_wr_addr_val_n,
                       ram256_wr_addr_val_n,
                       ram_data_in,
                       ram128_wr_n,
                       ram256_wr_n,
                       ram_rd_n,
                       int_sfr_addr,
                       int_sfr_data_out,
                       int_sfr_wr,
                       ext_sfr_addr,
                       ext_sfr_data_out,
                       ext_sfr_wr,
                       ext_sfr_rd,
                       sfr_data_in,
                       port_pin_reg_n,

                       int_ack,
                       int_clr,
                       int_rec,

                       cpu_temp1,
                       cpu_temp2,
                       cpu_temp3,
                       result,

                       pc_cnt_dir,
                       inc_pc,
                       set_pc_n,
                       pc_inc,
                       dp_inc,
                       pc_add_signed,
                       sel_pc_dptr_n,
    
                       sp_cnt_dir,
                       cnt_sp,

                       alu_op,
                       chg_flags,
                       acc_data,
                       ld_acc,
                       ld_acc_direct,

                       cpu_bit_nr
		       );

 input clk;
 input rst_n;
 input [1:0]  cycle;
 input [7:0]  biu_instr;
 input biu_ram_access_rdy;
 input int_req;
 input [3:0]  int_src;
 input [7:0]  alu;
 input [7:0]  alu_l;
 input [7:0]  sp;
 input [7:0]  dps;
 input [7:0]  pcon;
 input [7:0]  psw;
 input [7:0]  acc;
 input [7:0]  b;
 input [15:0]  dptr;
 input [7:0]  indir_data_in;
 input [15:0]  pc;
 input [15:0]  add16_sum;
 input eie_eip_check;
 input [7:0]  mpage;
 input [4:0] dec_itype;
 input [2:0] dec_last_cycle;
 input [3:0] dec_src;
 input [1:0] dec_src_cycle;
 input [3:0] dec_dest;
 input [5:0]  dec_alu_op;
 input dec_chg_flags;
 input dec_rmw;
 input alu_zero;
 input alu_equal;
 input bit_status;
 input [7:0]  sfr_data_in;
 output cpu_idle_mode_n;
 output cpu_stop_mode_n;
 output [15:0]  biu_ram_addr;
 output biu_wr_ram_addr_h;
 output biu_wr_ram_addr_l;
 output [7:0]  biu_data_out;
 output biu_wr_ram;
 output biu_rd_ram;
 output biu_rd_rom;
 output [7:0]  ram_addr;
 output ram128_wr_addr_val_n;
 output ram256_wr_addr_val_n;
 output [7:0]  ram_data_in;
 output ram128_wr_n;
 output ram256_wr_n;
 output ram_rd_n;
 output [7:0]  int_sfr_addr;
 output [7:0]  int_sfr_data_out;
 output int_sfr_wr;
 output [7:0]  ext_sfr_addr;
 output [7:0]  ext_sfr_data_out;
 output ext_sfr_wr;
 output ext_sfr_rd;
 output port_pin_reg_n;
 output int_ack;
 output int_clr;
 output int_rec;
 output [7:0]  cpu_temp1;
 output [7:0]  cpu_temp2;
 output [7:0]  cpu_temp3;
 output [15:0]  result;
 output pc_cnt_dir;
 output inc_pc;
 output set_pc_n;
 output [7:0]  pc_inc;
 output [7:0]  dp_inc;
 output pc_add_signed;
 output sel_pc_dptr_n;
 output sp_cnt_dir;
 output cnt_sp;
 output [5:0]  alu_op;
 output chg_flags;
 output [7:0]  acc_data;
 output ld_acc;
 output ld_acc_direct;
 output [7:0]  cpu_bit_nr;


//------------------------------------------------------------------------------
//                             DESCRIPTION
//------------------------------------------------------------------------------
//
// The DW8051_control module is the central module of the cpu. It controls the
// DW8051_biu (bus interface unit), the DW8051_op_decoder (opcode decoder),
// the DW8051_alu (arithmetic logical unit), handles all control flow of the
// different commands, interrupts and manages all read/write operations.
// All FF's are running on posedge of clk and reset asynchronously.
// Although there is only one main process (main_control_proc), basically there
// are managed 3 different tasks inside the process:
// a) handle all source (read) operations (source sequencer)
// b) handle all destination (write) operations (destination sequencer)
// c) handle the control flow of all opcodes (instruction sequencer)
//
//      src                             dest
//      1       accumulator             1       accumulator
//      2       register Rn             2       register Rn
//      3       direct data (2nd cycle) 3       direct data (type 1)
//      4       indirect @Ri (1Byte)    4       indirect @Ri (1Byte)
//      5       #data                   5       accu direct
//      6       ext RAM, @Ri            6       ext.RAM, @Ri
//      7       bit                     7       bit
//      8                               8       direct (type 2)
//      9                               9       direct (type 3)
//      10                              10      indirect (type 2)
//      11                              11      indirect (type 3)
//      12      @SP                     12      @SP
//      13                              13      dptr (src instr)
//      14      ROM                     14      dptr (src add16_sum)
//      15      ext.RAM, @DPTR          15      ext.RAM, @DPTR
//
//
// instruction type
//
//      One Cycle instructions:
// 0    none (default after reset)
// 0    NOP
// 1    RR A, INC A, INC @Ri, INC Rn, RRC A, DEC A, DEC @Ri, DEC Rn,
//      RL A, RLC A, CPL C, CLR C, SWAP A, SETB C, DA A, CLR A,
//      MOV A,@Ri, MOV A,Rn, CPL A, MOV @Ri,A, MOV Rn,A
// 1    XCH A,@Ri, XCH A,Rn, XCHD A,@Ri
// 2    idle_mode
// 3    ADD A,@Ri, ADD A,Rn, ADDC A,@Ri, ADDC A,Rn, ORL A,@Ri, ORL A,Rn,
//      ANL A,@Ri, ANL A,Rn, XRL A,@Ri, XRL A,Rn, SUBB A,@Ri, SUBB A,Rn
//
//      Two Cycle instructions:
// 4    ADD A,#data, ADD A,direct, ADDC A,#data, ADDC A,direct,
//      ORL direct,A, ORL A,#data, ORL A,direct, ANL direct,A,
//      ANL A,#data, ANL A,direct, XRL direct,A, XRL A,#data,
//      XRL A,direct, SUBB A,#data, SUBB A,direct
// 5    INC direct, DEC direct, MOV A,#data, MOV @Ri,#data,
//      MOV Rn,#data, MOV direct,@Ri, MOV direct,Rn, MOV bit,C,
//      MOV @Ri,direct, MOV Rn,direct, CPL bit, CLR bit, SETB bit,
//      MOV A,direct, MOV direct,A
// 5    XCH A,direct
// 6    ORL C,bit, ANL C,bit, ORL C,/bit, MOV C,bit, ANL C,/bit
// 7    PUSH, POP
// 8    MOVX A,@DPTR, MOVX A,@Ri, MOVX @DPTR,A, MOVX @Ri,A
//
//      Three Cycle instructions:
// 9    MOV direct,direct
// 10   MOV direct,#data
// 11   ORL direct,#data, ANL direct,#data, XRL direct,#data
// 12   INC DPTR
// 13   DJNZ Rn,rel
// 14   ACALL
// 15   AJMP
// 16   SJMP
// 17   JMP @A+DPTR
// 18   JC,JNC,JZ,JNZ
// 19   MOVC A,@A+PC, MOVC A,@A+DPTR
// 20   MOV DPTR,#data
//
//      Four Cycle instructions:
// 21   JBC, JB, JNB
// 22   CJNE A,#data,rel, CJNE A,direct,rel CJNE @Ri,#data,rel,
//      CJNE Rn,#data,rel
// 23   LCALL
// 24   LJMP
// 25   RET
// 25   RETI
// 26   DJNZ direct,rel
// 27   interrupts
//
//      Five Cycle instructions:
// 28   MUL AB
// 29   DIV AB
//
// itypes NOT used: 30,31
//
//
// Interrupts:
//          |c1|c2|c3|c4|c1|c2|c3|c4|c1| ... |c1|c2|c3|c4|
// int_req  xxxxxxxxxxxxxxxxxxx---xxxx       xxxxxxxxxxxxx
// int_ack  ______________________---_       _____________
// int_clr  __________________________       __________---_  (RETI)
// int_rec                       ^
//
//------------------------------------------------------------------------------

wire clk;
wire rst_n;
wire [1 : 0 ] cycle;
wire [7 : 0 ] biu_instr;
wire biu_ram_access_rdy;
wire int_req;
wire [ 3:0] int_src;
wire [ 7:0] alu;
wire [ 7:0] alu_l;
wire [ 7:0] sp;
wire [ 7:0] dps;
wire [ 7:0] pcon;
wire [ 7:0] psw;
wire [ 7:0] acc;
wire [ 7:0] b;