dw8051_serial.v

DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.

  // clock generation
  assign clk_div2 = ~cycle[0];
  assign sync_clk = (mode0         == 0)                       ? 0 :
                    (port_busy     == 1)                       ? 0 :
                    (legal_sbuf_wr == 1)                       ? 1 :
                    (scon_wr       == 0)                       ? 0 :
                  // ren goes high and ri is low and remains low
                    ((ren  == 0) & (serial_data_in[4] == 1) &
                     (i_ri == 0) & (serial_data_in[0] == 0))   ? 1 :
                  // ri goes low and ren is high and remains high
                    ((i_ri == 1) & (serial_data_in[0] == 0) &
                     (ren  == 1) & (serial_data_in[4] == 1))   ? 1 :
                  // ri goes low and ren goes high
                    ((i_ri == 1) & (serial_data_in[0] == 0) &
                     (ren  == 0) & (serial_data_in[4] == 1))   ? 1 :
                                                                 0;


  always @(posedge clk or negedge rst_n)
  begin : clk_div_process
    if (rst_n == 0)
    begin 
      count     <= 2'b00;
      clk_div12 <= 0;
    end
    else
    begin
      if (sync_clk == 1)
      begin 
        count     <= 2'b00;
        clk_div12 <= 0;
      end
      else if (cycle == `c3)
      begin 
        count[0]  <= ~(count[0] | count[1]);
        count[1]  <= count[0];
        clk_div12 <= count[1];
      end
      else clk_div12 <= 0;
    end 
  end  //clk_div_process


  always @(posedge clk or negedge rst_n)
  begin : t1_ofl_div_process
    if (rst_n == 0)
    begin 
      store_t1_ofl <= 0;
    end
    else
    begin
      if (t1_ofl == 1)
      begin 
        store_t1_ofl <= ~store_t1_ofl;
      end 
    end 
  end   //t1_ofl_div_process


  assign t_clk_x16    = (mode0 == 1)                        ? 0      :
                        ((smod == 1) | (store_t1_ofl == 0)) ? t1_ofl :
                                                            0;

  assign t_clk_x16_m2 =  (smod == 1)                   ? clk_div2 :
                        ((smod == 0) & (cycle == `c1)) ? 1        :
                                                         0;

  assign rx_t_clk_x16 = (mode2 == 1) ? t_clk_x16_m2 :
                        (rclk  == 0) ? t_clk_x16    :
                                       t2_ofl;

  assign tx_t_clk_x16 = (mode2 == 1) ? t_clk_x16_m2 :
                        (tclk  == 0) ? t_clk_x16    :
                                       t2_ofl;


  // input latches
  always @(posedge clk or negedge rst_n)
  begin : inp_latch_process
    if (rst_n == 0)
    begin 
      rxd_l0  <= 0;
      rxd_l0b <= 0;
      rxd_l1  <= 0;
      rxd_l2  <= 0;
      rxd_l3  <= 0;
    end
    else
    begin
      rxd_l0  <= rxd_in;
      rxd_l0b <= rxd_l0;
      if (rx_t_clk_x16 == 1)
      begin 
        if (mode1or3 == 1) rxd_l1 <= rxd_l0b;
        else               rxd_l1 <= rxd_l0;
      end 
      if (rx_t_clk_x16 == 1)
      begin 
        rxd_l2 <= rxd_l1;
        rxd_l3 <= rxd_l2;
      end 
    end 
  end  //inp_latch_process


  // detect high to low transition on rxd input
  assign  rxd_event   = rxd_l2 & ~rxd_l1;
  assign clr_rx_cnt_n = (rx_state == `rx_idle) ? ~rxd_event : 1;

  assign  mode_change = ((mode[0] ^ serial_data_in[6]) |
                         (mode[1] ^ serial_data_in[7])) & scon_wr;

  assign  ld_tx_cnt_n = ~(mode_change & serial_data_in[6]);


  // divide rx_t_clk_x16 by 16
  DW8051_updn_ctr #(4) u2
                    (.up_dn  (high),		// up counter
                     .load   (clr_rx_cnt_n),	// active low
                     .data   (low_4),
                     .cen    (rx_t_clk_x16),
                     .clk    (clk),
                     .reset  (rst_n),		// active low
                     .count  (rx_cnt),
                     .tercnt (rx_tercnt));

  // divide tx_t_clk_x16 by 16
  DW8051_updn_ctr #(4) u3
                    (.up_dn  (high),		// up counter
                     .load   (ld_tx_cnt_n),	// active low
                     .data   (tx_ld_data),
                     .cen    (tx_t_clk_x16),
                     .clk    (clk),
                     .reset  (rst_n),		// active low
                     .count  (tx_cnt),
                     .tercnt (tx_tercnt));


  always @ (posedge clk or negedge rst_n)
  begin : tx_m123_clk_process
    if (rst_n == 0)
    begin 
      tx_m123_clk <= 0;
    end
    else
    begin
      if ((tx_tercnt == 1) & (tx_t_clk_x16 == 1)) tx_m123_clk <= 1;
      else if (cycle == `c1)                      tx_m123_clk <= 0;
    end 
  end  //tx_m123_clk_process


  //----------------------------------------------------------------------------

  // generate output signals:
  always @(mode0 or cycle or sm2 or count or clk_div12)
  begin : shift_clk_process
    if (mode0 == 1)
    begin 
      if (sm2 == 1)
      begin 
        if ((cycle == `c1) | (cycle == `c4)) shift_clk <= 1;
        else                                 shift_clk <= 0;
      end
      else
      begin
        if (((cycle == `c3) & (count == 2'b10)) |
            (clk_div12 == 1) |
            ((cycle == `c1) & (count == 2'b00))) shift_clk <= 1;
        else                                     shift_clk <= 0;
      end 
    end
    else shift_clk <= 0;
  end  //shift_clk_process


  always @(posedge clk or negedge rst_n)
  begin : out_process
    if (rst_n == 0)
    begin 
      txd     <= 1;
      rxd_out <= 1;
    end
    else
    begin
      if (mode0 == 1) txd <= ((send | receive) & shift_clk) |
                              (~(send | receive));
      else            txd <= (data & tx_sbuf_reg[0]) | ~send;

      if ((mode0 == 1) & (send == 1)) rxd_out <= tx_sbuf_reg[0];
      else                            rxd_out <= 1;
    end 
  end  //out_process

  assign ri = i_ri;
  assign ti = i_ti;

  assign serial_sfr_cs  = scon_cs | sbuf_cs;

  assign serial_data_out = (sbuf_cs == 1) ? rx_sbuf_reg : scon_reg;

  //----------------------------------------------------------------------------
  // tx control:

  assign tx_clk = ((mode0 == 1) & (sm2 == 0))                  ? clk_div12   :
                  ((mode0 == 1) & (sm2 == 1) & (cycle == `c4)) ? 1           :
                  (cycle == `c1)                               ? tx_m123_clk :
                                                                 0;

  assign tx_shift_n = (tx_state == `tx_idle)                         ? 1 :
                      (tx_state == `tx_initialize)                   ? 1 :
                     ((tx_state == `tx_transfer_1st) & (mode0 == 0)) ? 1 :
                                                                       ~tx_clk;

  assign zero_det_n = (tx_sbuf_reg[9:2] != 8'b00000000) ? 1 : 0;

  assign  tx_ser_in = 0;

  assign send  = (tx_state == `tx_transfer_1st) ? 1 :
                 (tx_state == `tx_transfer)     ? 1 :
                                                  0;

  assign data  = (tx_state == `tx_transfer) ? 1 : 0;

  assign set_ti = ((mode0 == 1) & (tx_state == `tx_stop1) &
                   (cycle == `c3))                           ? 1 :
                  ((tx_state == `tx_stop2) & (cycle == `c3)) ? 1 :
                                                                0;

  assign stop_tx = (mode_change == 1) ? 1 : 0;


  always @(posedge clk or negedge rst_n)
  begin : tx_control_process
    if (rst_n == 0)
    begin 
      tx_state  <= `tx_idle;
    end
    else
    begin
      case (tx_state )
        `tx_idle        : begin
                            if (legal_sbuf_wr == 1) tx_state <= `tx_initialize;
                          end
        `tx_initialize  : begin
                                 if (stop_tx == 1) tx_state <= `tx_idle;
                            else if (tx_clk  == 1) tx_state <= `tx_transfer_1st;
                          end
        `tx_transfer_1st: begin
                                 if (stop_tx == 1) tx_state <= `tx_idle;
                            else if (tx_clk  == 1) tx_state <= `tx_transfer;
                          end
        `tx_transfer    : begin
                                 if (stop_tx == 1)      tx_state <= `tx_idle;
                            else if ((zero_det_n == 0) &
                                     (tx_shift_n == 0)) tx_state <= `tx_stop1;
                          end
        `tx_stop1       : begin
                                 if (stop_tx == 1) tx_state <= `tx_idle;
                            else if (cycle == `c3)
                            begin 
                              if (mode0 == 1) tx_state <= `tx_idle;
                              else            tx_state <= `tx_stop2;
                            end 
                          end
        `tx_stop2       : begin
                                 if (stop_tx == 1) tx_state <= `tx_idle;
                            else if (cycle == `c3) tx_state <= `tx_idle;
                          end
      endcase
    end 
  end  //tx_control_process

  //----------------------------------------------------------------------------
  // rx control:

  assign rx_clk = ((mode0 == 1) & (sm2 == 0))                  ? clk_div12 :
                  ((mode0 == 1) & (sm2 == 1) & (cycle == `c1)) ? 1         :
                                                                 rx_t_clk;

  assign rx_load_n  = ((rx_state == `rx_initialize) & (rx_clk == 1)) ? 0 : 1;

  assign rx_ser_in  = (mode0 == 1) ? rxd_l0 : rx_bit;

  assign rx_par_in  = (mode0 == 1) ? 9'b001111111 : 9'b011111111;

  assign receive    = (rx_state == `rx_transfer) ? 1 : 0;

  assign rx_shift_n = (rx_state == `rx_transfer) ? ~rx_clk    :
                      (mode0    == 1)            ? ~rx_accept :
                                                   1;

  assign rx_accept  = (ren == 0)                                       ? 0 :
                      ((mode0 == 1) & (cycle == `c3) &
                       (rx_state == `rx_stop))                         ? 1 :
                      (mode0 == 1)                                     ? 0 :
                      (cycle != `c1 )                                  ? 0 :
                      (~(((rx_state  == `rx_transfer) &
                          (rx_clk    == 1) &
                          (rx_reg[0] == 0)) | (rx_state == `rx_stop))) ? 0 :
                      (i_ri == 1)                                      ? 0 :
                      ((sm2 == 0) | (rx_bit == 1))                     ? 1 :
                                                                         0;

  // 2 of 3 majority
  assign rx_cmp_3  = (mode2 == 1) ? rxd_l3 : rxd_l0b;

  assign rx_bit = (rxd_l1 & rxd_l2) | (rxd_l2 & rx_cmp_3) | 
		  (rx_cmp_3 & rxd_l1);

  assign rx_t_clk = ((rx_cnt == 4'b1000) & (mode1or3 == 1)) ? rx_t_clk_x16 :
                    ((rx_cnt == 4'b1001) & (mode1or3 == 0)) ? rx_t_clk_x16 :
                                                              0;

  assign stop_rx  = (ren == 0)         ? 1 :
                    (mode_change == 1) ? 1 :
                                         0;



  always @(posedge clk or negedge rst_n)
  begin : rx_control_process
    if (rst_n == 0)
    begin 
      rx_update <= 0;
      rx_state  <= `rx_idle;
    end
    else
    begin
      rx_update <= rx_accept;

      case (rx_state)
        `rx_idle       : begin
                           if (mode0 == 1)
                           begin 
                             if ((ren == 1) & (i_ri == 0))
                               rx_state <= `rx_initialize;
                           end
                           else
                           begin
                             if ((rxd_event == 1) & (ren == 1))
                               rx_state <= `rx_initialize;
                           end 
                         end
        `rx_initialize : begin
                           if (stop_rx == 1) rx_state <= `rx_idle;
                           else if (rx_clk == 1)
                           begin 
                             if ((mode0 == 0) & (rx_bit == 1))
                                  rx_state <= `rx_idle;
                             else rx_state <= `rx_transfer;
                           end 
                         end
        `rx_transfer   : begin
                           if (stop_rx == 1) rx_state <= `rx_idle;
                           else if ((rx_reg[0] == 0) & (rx_clk == 1))
                           begin 
                             if ((mode0 == 1) | ~(cycle == `c1))
                                  rx_state <= `rx_stop;
                             else rx_state <= `rx_idle;
                           end 
                         end
        `rx_stop       : begin
                           if  ((stop_rx == 1) |
                                ((mode0 == 1) & (cycle == `c3)) |
                                ((mode0 == 0) & (cycle == `c1)))
                           begin 
                             rx_state  <= `rx_idle;
                           end 
                         end
      endcase
    end 
  end   //rx_control_process


endmodule