skgehw.h

移植到2410开发板上的源代码

#define	T2_STEP03	(1<<2)	/* Bit 2:	Inc AC/Dec BC by 3 */
#define	T2_STEP02	(1<<1)	/* Bit 1:	Inc AC/Dec BC by 2 */
#define	T2_STEP01	(1<<0)	/* Bit 0:	Inc AC/Dec BC by 1 */

/*	Q_T3	32 bit	Test Register 3	*/
							/* Bit 31..7:	reserved */
#define	T3_MUX		(7<<4)	/* Bit 6.. 4:	Mux Position */
							/* Bit 3:	reserved */
#define	T3_VRAM		(7<<0)	/* Bit 2.. 0:	Virtual RAM Buffer Address */

/* RAM Buffer Register Offsets */
/* use RB_ADDR(Queue,Offs) to address */
/*	RB_START	32 bit	RAM Buffer Start Address */
/*	RB_END		32 bit	RAM Buffer End Address */
/*	RB_WP		32 bit	RAM Buffer Write Pointer */
/*	RB_RP		32 bit	RAM Buffer Read Pointer */
/*	RB_RX_UTPP	32 bit	Rx Upper Threshold, Pause Pack */
/*	RB_RX_LTPP	32 bit	Rx Lower Threshold, Pasue Pack */
/*	RB_RX_UTHP	32 bit	Rx Upper Threshold, High Prio */
/*	RB_RX_LTHP	32 bit	Rx Lower Threshold, High Prio */
/*	RB_PC		32 bit	RAM Buffer Packet Counter */
/*	RB_LEV		32 bit	RAM Buffer Level Register */
				/* Bit 31..19:	reserved */
#define RB_MSK	0x0007ffff	/* Bit 18.. 0:	RAM Buffer Pointer Bits */

/*	RB_TST2		8 bit	RAM Buffer Test Register 2 */
							/* Bit 4..7:	reserved */
#define	RB_PC_DEC	(1<<3)	/* Bit 3:	Packet Counter Decrem */
#define RB_PC_T_ON	(1<<2)	/* Bit 2:	Packet Counter Test On */
#define RB_PC_T_OFF	(1<<1)	/* Bit 1:	Packet Counter Tst Off */
#define RB_PC_INC	(1<<0)	/* Bit 0:	Packet Counter Increm */

/*	RB_TST1		8 bit	RAM Buffer Test Register 1 */
				/* Bit 7:	reserved */
#define RB_WP_T_ON	(1<<6)	/* Bit 6:	Write Pointer Test On */
#define RB_WP_T_OFF	(1<<5)	/* Bit 5:	Write Pointer Test Off */
#define RB_WP_INC	(1<<4)	/* Bit 4:	Write Pointer Increm */
							/* Bit 3:	reserved */
#define RB_RP_T_ON	(1<<2)	/* Bit 2:	Read Pointer Test On */
#define RB_RP_T_OFF	(1<<1)	/* Bit 1:	Read Pointer Test Off */
#define RB_RP_DEC	(1<<0)	/* Bit 0:	Read Pointer Decrement */

/*	RB_CTRL		8 bit	RAM Buffer Control Register */
								/* Bit	7..6:	reserved */
#define RB_ENA_STFWD	(1<<5)	/* Bit	5:	Enable Store & Forward */
#define RB_DIS_STFWD	(1<<4)	/* Bit	4:	Disab. Store & Forward */
#define RB_ENA_OP_MD	(1<<3)	/* Bit	3:	Enable Operation Mode */
#define RB_DIS_OP_MD	(1<<2)	/* Bit	2:	Disab. Operation Mode */
#define RB_RST_CLR		(1<<1)	/* Bit	1:	Clr RAM Buf STM Reset */
#define RB_RST_SET		(1<<0)	/* Bit	0:	Set RAM Buf STM Reset */


/* Receive and Transmit MAC FIFO Registers, use MR_ADDR() to address */
/*	RX_MFF_EA	32 bit	Receive MAC FIFO End Address */
/*	RX_MFF_WP	32 bit 	Receive MAC FIFO Write Pointer */
/*	RX_MFF_RP	32 bit	Receive MAC FIFO Read Pointer */
/*	RX_MFF_PC	32 bit	Receive MAC FIFO Packet Counter*/
/*	RX_MFF_LEV	32 bit	Receive MAC FIFO Level */
/*	TX_MFF_EA	32 bit	Transmit MAC FIFO End Address */
/*	TX_MFF_WP	32 bit 	Transmit MAC FIFO Write Pointer*/
/*	TX_MFF_WSP	32 bit	Transmit MAC FIFO WR Shadow Pt*/
/*	TX_MFF_RP	32 bit	Transmit MAC FIFO Read Pointer */
/*	TX_MFF_PC	32 bit	Transmit MAC FIFO Packet Cnt */
/*	TX_MFF_LEV	32 bit	Transmit MAC FIFO Level */
							/* Bit 31..6:	reserved */
#define MFF_MSK		0x007fL	/* Bit	5..0:	MAC FIFO Address/Pointer Bits */

/*	RX_MFF_CTRL1	16 bit	Receive MAC FIFO Control Reg 1 */
									/* Bit 15..14:	reserved */
#define MFF_ENA_RDY_PAT	(1<<13)		/* Bit 13:	Enable Ready Patch */
#define MFF_DIS_RDY_PAT	(1<<12)		/* Bit 12:	Disable Ready Patch */
#define MFF_ENA_TIM_PAT	(1<<11)		/* Bit 11:	Enable Timing Patch */
#define MFF_DIS_TIM_PAT	(1<<10)		/* Bit 10:	Disable Timing Patch */
#define MFF_ENA_ALM_FUL	(1<<9)		/* Bit	9:	Enable AlmostFull Sign*/
#define MFF_DIS_ALM_FUL	(1<<8)		/* Bit	8:	Disab. AlmostFull Sign*/
#define MFF_ENA_PAUSE	(1<<7)		/* Bit	7:	Enable Pause Signaling*/
#define MFF_DIS_PAUSE	(1<<6)		/* Bit	6:	Disab. Pause Signaling*/
#define MFF_ENA_FLUSH	(1<<5)		/* Bit	5:	Enable Frame Flushing */
#define MFF_DIS_FLUSH	(1<<4)		/* Bit	4:	Disab. Frame Flushing */
#define MFF_ENA_TIST	(1<<3)		/* Bit	3:	Enable Timestamp Gener*/
#define MFF_DIS_TIST	(1<<2)		/* Bit	2:	Disab. Timestamp Gener*/
#define MFF_CLR_INTIST	(1<<1)		/* Bit	1:	Clear IRQ No Timestamp*/
#define MFF_CLR_INSTAT	(1<<0)		/* Bit	0:	Clear IRQ No Status */

#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT

/*	TX_MFF_CTRL1	16 bit	Transmit MAC FIFO Control Reg 1 */
#define MFF_CLR_PERR	(1<<15)		/* Bit 15:	Clear Parity Error IRQ*/
									/* Bit 14:	reserved */
#define MFF_ENA_PKT_REC	(1<<13)		/* Bit 13:	Enable Packet Recovery*/
#define MFF_DIS_PKT_REC (1<<12)		/* Bit 12:	Disable Packet Recov. */
/*	MFF_ENA_TIM_PAT	 (see RX_MFF_CTRL1)Bit 11:	Enable Timing Patch */
/*	MFF_DIS_TIM_PAT	 (see RX_MFF_CTRL1)Bit 10:	Disable Timing Patch */
/*	MFF_ENA_ALM_FUL	 (see RX_MFF_CTRL1)Bit	9:	Enable AlmostFull Sign*/
/*	MFF_DIS_ALM_FUL	 (see RX_MFF_CTRL1)Bit	8:	Disab. AlmostFull Sign*/
#define	MFF_ENA_W4E		(1<<7)		/* Bit	7:	Enable Wait for Empty */
#define MFF_DIS_W4E		(1<<6)		/* Bit	6:	Disab. Wait for Empty */
/*	MFF_ENA_FLUSH	 (see RX_MFF_CTRL1)Bit	5:	Enable Frame Flushing */
/*	MFF_DIS_FLUSH	 (see RX_MFF_CTRL1)Bit	4:	Disab. Frame Flushing */
#define MFF_ENA_LOOPB	(1<<3)		/* Bit	3:	Enable Loopback */
#define MFF_DIS_LOOPB	(1<<2)		/* Bit	2:	Disable Loopback */
#define MFF_CLR_MAC_RST	(1<<1)		/* Bit	1:	Clear XMAC Reset */
#define MFF_SET_MAC_RST	(1<<0)		/* Bit	0:	Set XMAC Reset */

#define MFF_TX_CTRL_DEF	(MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)

/*	RX_MFF_TST2	 8 bit	Receive MAC FIFO Test Register 2 */
/*	TX_MFF_TST2	 8 bit	Transmit MAC FIFO Test Register 2 */
								/* Bit 7:	reserved */
#define MFF_WSP_T_ON	(1<<6)	/* Bit 6: (Tx)	Write Shadow Pt TestOn */
#define MFF_WSP_T_OFF	(1<<5)	/* Bit 5: (Tx)	Write Shadow Pt TstOff */
#define MFF_WSP_INC		(1<<4)	/* Bit 4: (Tx)	Write Shadow Pt Increm */
#define	MFF_PC_DEC		(1<<3)	/* Bit 3:	Packet Counter Decrem  */
#define MFF_PC_T_ON		(1<<2)	/* Bit 2:	Packet Counter Test On */
#define MFF_PC_T_OFF	(1<<1)	/* Bit 1:	Packet Counter Tst Off */
#define MFF_PC_INC		(1<<0)	/* Bit 0:	Packet Counter Increm  */

/*	RX_MFF_TST1	 8 bit	Receive MAC FIFO Test Register 1 */
/*	TX_MFF_TST1	 8 bit	Transmit MAC FIFO Test Register 1 */
					/* Bit 7:	reserved */
#define MFF_WP_T_ON		(1<<6)	/* Bit 6:	Write Pointer Test On */
#define MFF_WP_T_OFF	(1<<5)	/* Bit 5:	Write Pointer Test Off */
#define MFF_WP_INC		(1<<4)	/* Bit 4:	Write Pointer Increm */
								/* Bit 3:	reserved */
#define MFF_RP_T_ON		(1<<2)	/* Bit 2:	Read Pointer Test On */
#define MFF_RP_T_OFF	(1<<1)	/* Bit 1:	Read Pointer Test Off */
#define MFF_RP_DEC		(1<<0)	/* Bit 0:	Read Pointer Decrement */

/*	RX_MFF_CTRL2	 8 bit	Receive MAC FIFO Control Reg 2 */
/*	TX_MFF_CTRL2	 8 bit	Transmit MAC FIFO Control Reg 2 */
								/* Bit 7..4:	reserved */
#define MFF_ENA_OP_MD	(1<<3)	/* Bit 3:	Enable Operation Mode */
#define MFF_DIS_OP_MD	(1<<2)	/* Bit 2:	Disab. Operation Mode */
#define MFF_RST_CLR		(1<<1)	/* Bit 1:	Clear MAC FIFO Reset */
#define MFF_RST_SET		(1<<0)	/* Bit 0:	Set MAC FIFO Reset */


/* Receive, Transmit, and Link LED Counter Registers */
/*	RX_LED_CTRL		8 bit	Receive LED Cnt Control Reg */
/*	TX_LED_CTRL		8 bit	Transmit LED Cnt Control Reg */
/*	LNK_SYNC_CTRL	8 bit	Link Sync Cnt Control Register */
							/* Bit 7..3:	reserved */
#define LED_START	(1<<2)	/* Bit 2:	Start Timer */
#define LED_STOP	(1<<1)	/* Bit 1:	Stop Timer */
#define LED_STATE	(1<<0)	/* Bit 0:(Rx/Tx)LED State, 1=LED on */
#define LED_CLR_IRQ	(1<<0)	/* Bit 0:(Lnk) 	Clear Link IRQ */

/*	RX_LED_TST		8 bit	Receive LED Cnt Test Register */
/*	TX_LED_TST		8 bit	Transmit LED Cnt Test Register */
/*	LNK_SYNC_TST	8 bit	Link Sync Cnt Test Register */
							/* Bit 7..3:	reserved */
#define LED_T_ON	(1<<2)	/* Bit 2:	LED Counter Testmode On */
#define LED_T_OFF	(1<<1)	/* Bit 1:	LED Counter Testmode Off */
#define LED_T_STEP	(1<<0)	/* Bit 0:	LED Counter Step */

/*	LNK_LED_REG	 8 bit	Link LED Register */
								/* Bit 7..6:	reserved */
#define LED_BLK_ON		(1<<5)	/* Bit 5:	Link LED Blinking On */
#define LED_BLK_OFF		(1<<4)	/* Bit 4:	Link LED Blinking Off */
#define LED_SYNC_ON		(1<<3)	/* Bit 3:	Use Sync Wire to switch LED */
#define LED_SYNC_OFF	(1<<2)	/* Bit 2:	Disable Sync Wire Input */
#define LED_ON			(1<<1)	/* Bit 1:	switch LED on */
#define LED_OFF			(1<<0)	/* Bit 0:	switch LED off */


/* Receive and Transmit Descriptors ******************************************/

/* Transmit Descriptor struct */
typedef	struct s_HwTxd {
	SK_U32 volatile	TxCtrl;	/* Transmit Buffer Control Field */
	SK_U32	TxNext;			/* Physical Address Pointer to the next TxD */
	SK_U32	TxAdrLo;		/* Physical Tx Buffer Address lower dword */
	SK_U32	TxAdrHi;		/* Physical Tx Buffer Address upper dword */
	SK_U32	TxStat;			/* Transmit Frame Status Word */
#ifndef	SK_USE_REV_DESC
	SK_U16	TxTcpOffs;		/* TCP Checksum Calculation Start Value */
	SK_U16	TxRes1;			/* 16 bit reserved field */
	SK_U16	TxTcpWp;		/* TCP Checksum Write Position */
	SK_U16	TxTcpSp;		/* TCP Checksum Calculation Start Position */
#else	/* SK_USE_REV_DESC */
	SK_U16	TxRes1;			/* 16 bit reserved field */
	SK_U16	TxTcpOffs;		/* TCP Checksum Calculation Start Value */
	SK_U16	TxTcpSp;		/* TCP Checksum Calculation Start Position */
	SK_U16	TxTcpWp;		/* TCP Checksum Write Position */
#endif	/* SK_USE_REV_DESC */
	SK_U32  TxRes2;			/* 32 bit reserved field */
} SK_HWTXD;

/* Receive Descriptor struct */
typedef	struct s_HwRxd {
	SK_U32 volatile RxCtrl;	/* Receive Buffer Control Field */
	SK_U32	RxNext;		/* Physical Address Pointer to the next TxD */
	SK_U32	RxAdrLo;	/* Physical Receive Buffer Address lower dword*/
	SK_U32	RxAdrHi;	/* Physical Receive Buffer Address upper dword*/
	SK_U32	RxStat;		/* Receive Frame Status Word */
	SK_U32	RxTiSt;		/* Receive Timestamp provided by the XMAC */
#ifndef	SK_USE_REV_DESC	
	SK_U16	RxTcpSum1;	/* TCP Checksum 1 */
	SK_U16	RxTcpSum2;	/* TCP Checksum 2 */
	SK_U16	RxTcpSp1;	/* TCP Checksum Calculation Start Position 1 */
	SK_U16	RxTcpSp2;	/* TCP Checksum Calculation Start Position 2 */
#else	/* SK_USE_REV_DESC */
	SK_U16	RxTcpSum2;	/* TCP Checksum 2 */
	SK_U16	RxTcpSum1;	/* TCP Checksum 1 */
	SK_U16	RxTcpSp2;	/* TCP Checksum Calculation Start Position 2 */
	SK_U16	RxTcpSp1;	/* TCP Checksum Calculation Start Position 1 */
#endif	/* SK_USE_REV_DESC */
} SK_HWRXD;

/*
 * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
 * should set the define SK_USE_REV_DESC.
 * Structures are 'normaly' not endianess dependent. But in 
 * this case the SK_U16 fields are bound to bit positions inside the
 * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
 * The bit positions inside a DWord are of course endianess dependent and
 * swaps if the DWord is swaped by the hardware.
 */


/* Descriptor Bit Definition */
/*	TxCtrl		Transmit Buffer Control Field */
/*	RxCtrl		Receive Buffer Control Field */
#define	BMU_OWN			(1UL<<31)	/* Bit 31:	OWN bit: 0=host/1=BMU */
#define	BMU_STF			(1L<<30)	/* Bit 30:	Start of Frame ? */
#define	BMU_EOF			(1L<<29)	/* Bit 29:	End of Frame ?	*/
#define	BMU_IRQ_EOB		(1L<<28)	/* Bit 28:	Req "End of Buff" IRQ */
#define	BMU_IRQ_EOF		(1L<<27)	/* Bit 27:	Req "End of Frame" IRQ*/
/* TxCtrl specific bits */
#define BMU_STFWD		(1L<<26)	/* Bit 26: (Tx)	Store&Forward Frame */
#define BMU_NO_FCS		(1L<<25)	/* Bit 25: (Tx) disable XMAC FCS gener*/
#define BMU_SW			(1L<<24)	/* Bit 24: (Tx)	1 bit res. for SW use */
/* RxCtrl specific bits */
#define	BMU_DEV_0		(1L<<26)	/* Bit 26: (Rx)	transfer data to Dev0 */
#define BMU_STAT_VAL	(1L<<25)	/* Bit 25: (Rx)	RxStat Valid */
#define BMU_TIST_VAL	(1L<<24)	/* Bit 24: (Rx)	RxTiSt Valid */
									/* Bit 23..16:	BMU Check Opcodes */
#define	BMU_CHECK		0x00550000L	/* 		Default BMU check */
#define	BMU_TCP_CHECK	0x00560000L	/* 		Descr with TCP ext */
#define	BMU_BBC			0x0000FFFFL	/* Bit 15..0:	Buffer Byte Counter */

/*	TxStat		Transmit Frame Status Word */
/*	RxStat		Receive Frame Status Word */
/*
 *Note: TxStat is reserved for ASIC loopback mode only
 *
 *	The Bits of the Status words are defined in xmac_ii.h
 *	(see XMR_FS bits)
 */

/* other defines *************************************************************/

/*
 * FlashProm specification
 */
#define	MAX_PAGES	0x20000L	/* Every byte has a single page */
#define	MAX_FADDR	1			/* 1 byte per page */
#define	SKFDDI_PSZ	8			/* address PROM size */

/* macros ********************************************************************/

/*
 * Receive and Transmit Queues
 */
#define Q_R1	0x0000		/* Receive Queue 1 */
#define Q_R2	0x0080		/* Receive Queue 2 */
#define Q_XS1	0x0200		/* Synchronous Transmit Queue 1 */
#define Q_XA1	0x0280		/* Asynchronous Transmit Queue 1 */
#define Q_XS2	0x0300		/* Synchronous Transmit Queue 2 */
#define Q_XA2	0x0380		/* Asynchronous Transmit Queue 2 */

/*
 *	Macro Q_ADDR()
 *
 *	Use this macro to address the Receive and Transmit Queue Registers.
 *
 * para	Queue	Queue to address.
 *			Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
 *	Offs	Queue register offset.
 *			Values: Q_D, Q_DA_L ... Q_T2, Q_T3
 *
 * usage	SK_IN32(pAC,Q_ADDR(Q_R2,Q_BC),pVal)
 */
#define Q_ADDR(Queue,Offs)	(B8_Q_REGS + (Queue) + (Offs))

/*
 *	Macro RB_ADDR()
 *
 *	Use this macro to address the RAM B